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Message-ID: <20220628160001.000021c5@Huawei.com>
Date: Tue, 28 Jun 2022 16:00:01 +0100
From: Jonathan Cameron <Jonathan.Cameron@...wei.com>
To: <ira.weiny@...el.com>
CC: Dan Williams <dan.j.williams@...el.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Lukas Wunner <lukas@...ner.de>,
Alison Schofield <alison.schofield@...el.com>,
Vishal Verma <vishal.l.verma@...el.com>,
"Dave Jiang" <dave.jiang@...el.com>,
Ben Widawsky <bwidawsk@...nel.org>,
<linux-kernel@...r.kernel.org>, <linux-cxl@...r.kernel.org>,
<linux-pci@...r.kernel.org>
Subject: Re: [PATCH V12 9/9] cxl/port: Parse out DSMAS data from CDAT table
On Mon, 27 Jun 2022 21:15:27 -0700
ira.weiny@...el.com wrote:
> From: Ira Weiny <ira.weiny@...el.com>
>
> CXL Ports with memory devices attached need the information from the
> Device Scoped Memory Affinity Structure (DSMAS). This information is
> contained within the CDAT table buffer which is cached in the port
> device.
>
> If CDAT data is available, parse and cache DSMAS data from the table.
> Store this data in unmarshaled struct dsmas data structures for ease of
> use later. Ensure DSMAS headers are not malicious or ill formed so as
> to cause buffer overflow errors.
>
> Signed-off-by: Ira Weiny <ira.weiny@...el.com>
>
Looks good to me. Was kind of expecting yet another xarray :)
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@...wei.com>
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