linux-kernel - [PATCH v3 2/2] mtd: rawnand: arasan: Fix clock rate in NV-DDR

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Date:   Tue, 28 Jun 2022 21:18:24 +0530
From:   Amit Kumar Mahapatra <amit.kumar-mahapatra@...inx.com>
To:     <miquel.raynal@...tlin.com>, <nagasure@...inx.com>,
        <vigneshr@...com>
CC:     <boris.brezillon@...labora.com>, <linux-mtd@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <git@....com>, <richard@....at>,
        <amit.kumar-mahapatra@....com>, Olga Kitaina <okitain@...il.com>,
        <stable@...r.kernel.org>,
        Amit Kumar Mahapatra <amit.kumar-mahapatra@...inx.com>
Subject: [PATCH v3 2/2] mtd: rawnand: arasan: Fix clock rate in NV-DDR

From: Olga Kitaina <okitain@...il.com>

According to the Arasan NAND controller spec, the flash clock rate for SDR
must be <= 100 MHz, while for NV-DDR it must be the same as the rate of the
CLK line for the mode. The driver previously always set 100 MHz for NV-DDR,
which would result in incorrect behavior for NV-DDR modes 0-4.

The appropriate clock rate can be calculated from the NV-DDR timing
parameters as 1/tCK, or for rates measured in picoseconds,
10^12 / nand_nvddr_timings->tCK_min.

Fixes: 197b88fecc50 ("mtd: rawnand: arasan: Add new Arasan NAND controller")
CC: stable@...r.kernel.org # 5.8+
Signed-off-by: Olga Kitaina <okitain@...il.com>
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@...inx.com>
---
 drivers/mtd/nand/raw/arasan-nand-controller.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/raw/arasan-nand-controller.c b/drivers/mtd/nand/raw/arasan-nand-controller.c
index c5264fa223c4..d4121d1243bf 100644
--- a/drivers/mtd/nand/raw/arasan-nand-controller.c
+++ b/drivers/mtd/nand/raw/arasan-nand-controller.c
@@ -1043,7 +1043,13 @@ static int anfc_setup_interface(struct nand_chip *chip, int target,
 				 DQS_BUFF_SEL_OUT(dqs_mode);
 	}
 
-	anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK;
+	if (nand_interface_is_sdr(conf)) {
+		anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK;
+	} else {
+		/* ONFI timings are defined in picoseconds */
+		anand->clk =  div_u64((u64)NSEC_PER_SEC * 1000,
+				      conf->timings.nvddr.tCK_min);
+	}
 
 	/*
 	 * Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1 work
-- 
2.17.1