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Message-ID: <SN6PR12MB27677062FBBF9D62C7BF41D88EB89@SN6PR12MB2767.namprd12.prod.outlook.com>
Date: Tue, 28 Jun 2022 17:57:41 +0000
From: "Kalra, Ashish" <Ashish.Kalra@....com>
To: "Dr. David Alan Gilbert" <dgilbert@...hat.com>
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Subject: RE: [PATCH Part2 v6 06/49] x86/sev: Add helper functions for
RMPUPDATE and PSMASH instruction
[AMD Official Use Only - General]
Hello Dave,
-----Original Message-----
From: Dr. David Alan Gilbert <dgilbert@...hat.com>
Sent: Tuesday, June 28, 2022 5:51 AM
To: Kalra, Ashish <Ashish.Kalra@....com>
Cc: x86@...nel.org; linux-kernel@...r.kernel.org; kvm@...r.kernel.org; linux-coco@...ts.linux.dev; linux-mm@...ck.org; linux-crypto@...r.kernel.org; tglx@...utronix.de; mingo@...hat.com; jroedel@...e.de; Lendacky, Thomas <Thomas.Lendacky@....com>; hpa@...or.com; ardb@...nel.org; pbonzini@...hat.com; seanjc@...gle.com; vkuznets@...hat.com; jmattson@...gle.com; luto@...nel.org; dave.hansen@...ux.intel.com; slp@...hat.com; pgonda@...gle.com; peterz@...radead.org; srinivas.pandruvada@...ux.intel.com; rientjes@...gle.com; dovmurik@...ux.ibm.com; tobin@....com; bp@...en8.de; Roth, Michael <Michael.Roth@....com>; vbabka@...e.cz; kirill@...temov.name; ak@...ux.intel.com; tony.luck@...el.com; marcorr@...gle.com; sathyanarayanan.kuppuswamy@...ux.intel.com; alpergun@...gle.com; jarkko@...nel.org
Subject: Re: [PATCH Part2 v6 06/49] x86/sev: Add helper functions for RMPUPDATE and PSMASH instruction
* Kalra, Ashish (Ashish.Kalra@....com) wrote:
> [AMD Official Use Only - General]
>
> >>> /*
> >>> * The RMP entry format is not architectural. The format is
> >>> defined in PPR @@ -126,6 +128,15 @@ struct snp_guest_platform_data {
> >>> u64 secrets_gpa;
> >>> };
> >>>
> >>> +struct rmpupdate {
> >>> + u64 gpa;
> >>> + u8 assigned;
> >>> + u8 pagesize;
> >>> + u8 immutable;
> >>> + u8 rsvd;
> >>> + u32 asid;
> >>> +} __packed;
>
> >>I see above it says the RMP entry format isn't architectural; is this 'rmpupdate' structure? If not how is this going to get handled when we have a couple >of SNP capable CPUs with different layouts?
>
> >Architectural implies that it is defined in the APM and shouldn't change in such a way as to not be backward compatible.
> >I probably think the wording here should be architecture independent or more precisely platform independent.
>
> Some more clarity on this:
>
> Actually, the PPR for family 19h Model 01h, Rev B1 defines the RMP entry format as below:
>
> 2.1.4.2 RMP Entry Format
> Architecturally the format of RMP entries are not specified in APM. In order to assist software, the following table specifies select portions of the RMP entry format for this specific product. Each RMP entry is 16B in size and is formatted as follows. Software should not rely on any field definitions not specified in this table and the format of an RMP entry may change in future processors.
>
> Architectural implies that it is defined in the APM and shouldn't change in such a way as to not be backward compatible. So non-architectural in this context means that it is only defined in our PPR.
>
> So actually this RPM entry definition is platform dependent and will need to be changed for different AMD processors and that change has to be handled correspondingly in the dump_rmpentry() code.
> You'll need a way to make that fail cleanly when run on a newer CPU with different layout, and a way to build kernels that can handle more than one layout.
Yes, I will be adding a check for CPU family/model as following :
static int __init snp_rmptable_init(void)
{
+ int family, model;
if (!boot_cpu_has(X86_FEATURE_SEV_SNP))
return 0;
+ family = boot_cpu_data.x86;
+ model = boot_cpu_data.x86_model;
+ /*
+ * RMP table entry format is not architectural and it can vary by processor and
+ * is defined by the per-processor PPR. Restrict SNP support on the known CPU
+ * model and family for which the RMP table entry format is currently defined for.
+ */
+ if (family != 0x19 || model > 0xaf)
+ goto nosnp;
+
This way SNP will only be enabled specifically on the platforms for which this RMP entry
format is defined in those processor's PPR. This will work for Milan and Genoa as of now.
Additionally as per Sean's suggestion, I will be moving the RMP structure definition to sev.c,
which will make it a private structure and not exposed to other parts of the kernel.
Also in the future we will have an architectural interface to read the RMP table entry,
we will first check for it's availability and if not available fall back to the RMP table
entry structure definition.
Thanks,
Ashish
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