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Message-ID: <20220628054518.350717-1-j-choudhary@ti.com>
Date: Tue, 28 Jun 2022 11:15:18 +0530
From: Jayesh Choudhary <j-choudhary@...com>
To: <devicetree@...r.kernel.org>
CC: <nm@...com>, <vigneshr@...com>, <kristo@...nel.org>,
<robh+dt@...nel.org>, <krzysztof.kozlowski+dt@...aro.org>,
<j-choudhary@...com>, <linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>
Subject: [PATCH] arm64: dts: ti: k3-j721s2-main: Enable crypto accelerator
Add the node for SA2UL for supporting hardware crypto algorithms,
including SHA1, SHA256, SHA512, AES, 3DES and AEAD suites.
Signed-off-by: Jayesh Choudhary <j-choudhary@...com>
---
There is a dependency of this patch on a dmaengine patch:
<https://lore.kernel.org/all/20220628050232.331956-1-j-choudhary@ti.com/>
This patch adds the PSIL threads for main domain SA2UL.
Without the above patch, dma-controller fails to get the channel
and tcrypt module does software crypto. But it does not break boot
since its runtime and not compile-time.
Testing log: <https://gist.github.com/Jayesh2000/e429c78a545809602e6473886a2a6ae4>
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 34e7d577ae13..79ca34a7e34f 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -72,6 +72,20 @@
pinctrl-single,function-mask = <0xffffffff>;
};
+ main_crypto: crypto@...0000 {
+ compatible = "ti,j721e-sa2ul";
+ reg = <0x00 0x4e00000 0x00 0x1200>;
+ power-domains = <&k3_pds 297 TI_SCI_PD_SHARED>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
+
+ dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
+ <&main_udmap 0x4a41>;
+ dma-names = "tx", "rx1", "rx2";
+ dma-coherent;
+ };
+
main_uart0: serial@...0000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x200>;
--
2.17.1
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