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Message-Id: <20220629155956.1138955-18-nfraprado@collabora.com>
Date: Wed, 29 Jun 2022 11:59:54 -0400
From: Nícolas F. R. A. Prado
<nfraprado@...labora.com>
To: Matthias Brugger <matthias.bgg@...il.com>
Cc: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>, kernel@...labora.com,
Chen-Yu Tsai <wenst@...omium.org>,
Nícolas F. R. A. Prado
<nfraprado@...labora.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-mediatek@...ts.infradead.org
Subject: [PATCH v4 17/19] arm64: dts: mediatek: asurada: Enable MMC
Enable both MMC controllers present on Asurada. MMC0 is for
non-removable internal memory, while MMC1 is an SD card slot. MMC1 isn't
used on all machines, but in those cases the CD interrupt is never
triggered and thus it is basically as if it was disabled.
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@...labora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
---
Changes in v4:
- Added this patch
.../boot/dts/mediatek/mt8192-asurada.dtsi | 149 ++++++++++++++++++
1 file changed, 149 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
index d56c73e37633..7b89f6e552c5 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
@@ -170,6 +170,46 @@ &i2c7 {
pinctrl-0 = <&i2c7_pins>;
};
+&mmc0 {
+ status = "okay";
+
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_default_pins>;
+ pinctrl-1 = <&mmc0_uhs_pins>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
+ vqmmc-supply = <&mt6359_vufs_ldo_reg>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ supports-cqe;
+ cap-mmc-hw-reset;
+ mmc-hs400-enhanced-strobe;
+ hs400-ds-delay = <0x12814>;
+ no-sdio;
+ no-sd;
+ non-removable;
+};
+
+&mmc1 {
+ status = "okay";
+
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc1_default_pins>;
+ pinctrl-1 = <&mmc1_uhs_pins>;
+ bus-width = <4>;
+ max-frequency = <200000000>;
+ cd-gpios = <&pio 17 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <&mt6360_ldo5_reg>;
+ vqmmc-supply = <&mt6360_ldo3_reg>;
+ cap-sd-highspeed;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ no-sdio;
+ no-mmc;
+};
+
/* for CORE */
&mt6359_vgpu11_buck_reg {
regulator-always-on;
@@ -503,6 +543,115 @@ pins-bus {
};
};
+ mmc0_default_pins: mmc0-default-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-clk {
+ pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ mmc0_uhs_pins: mmc0-uhs-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO184__FUNC_MSDC0_DAT0>,
+ <PINMUX_GPIO188__FUNC_MSDC0_DAT1>,
+ <PINMUX_GPIO185__FUNC_MSDC0_DAT2>,
+ <PINMUX_GPIO193__FUNC_MSDC0_DAT3>,
+ <PINMUX_GPIO186__FUNC_MSDC0_DAT4>,
+ <PINMUX_GPIO189__FUNC_MSDC0_DAT5>,
+ <PINMUX_GPIO187__FUNC_MSDC0_DAT6>,
+ <PINMUX_GPIO190__FUNC_MSDC0_DAT7>,
+ <PINMUX_GPIO183__FUNC_MSDC0_CMD>;
+ input-enable;
+ drive-strength = <10>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-clk {
+ pinmux = <PINMUX_GPIO192__FUNC_MSDC0_CLK>;
+ drive-strength = <10>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-rst {
+ pinmux = <PINMUX_GPIO194__FUNC_MSDC0_RSTB>;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-ds {
+ pinmux = <PINMUX_GPIO191__FUNC_MSDC0_DSL>;
+ drive-strength = <10>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+ };
+
+ mmc1_default_pins: mmc1-default-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>,
+ <PINMUX_GPIO56__FUNC_MSDC1_DAT1>,
+ <PINMUX_GPIO55__FUNC_MSDC1_DAT2>,
+ <PINMUX_GPIO53__FUNC_MSDC1_DAT3>,
+ <PINMUX_GPIO52__FUNC_MSDC1_CMD>;
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-clk {
+ pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ pins-insert {
+ pinmux = <PINMUX_GPIO17__FUNC_GPIO17>;
+ input-enable;
+ bias-pull-up;
+ };
+ };
+
+ mmc1_uhs_pins: mmc1-uhs-pins {
+ pins-cmd-dat {
+ pinmux = <PINMUX_GPIO54__FUNC_MSDC1_DAT0>,
+ <PINMUX_GPIO56__FUNC_MSDC1_DAT1>,
+ <PINMUX_GPIO55__FUNC_MSDC1_DAT2>,
+ <PINMUX_GPIO53__FUNC_MSDC1_DAT3>,
+ <PINMUX_GPIO52__FUNC_MSDC1_CMD>;
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ pins-clk {
+ pinmux = <PINMUX_GPIO51__FUNC_MSDC1_CLK>;
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+ };
+
pcie_pins: pcie-default-pins {
pins-pcie-wake {
pinmux = <PINMUX_GPIO63__FUNC_PCIE_WAKE_N>;
--
2.36.1
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