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Message-ID: <3656a067-cc3f-fd5b-e339-5925a856cce1@microchip.com>
Date:   Wed, 29 Jun 2022 18:18:25 +0000
From:   <Conor.Dooley@...rochip.com>
To:     <sudeep.holla@....com>, <linux-kernel@...r.kernel.org>
CC:     <gregkh@...uxfoundation.org>, <atishp@...shpatra.org>,
        <atishp@...osinc.com>, <vincent.guittot@...aro.org>,
        <dietmar.eggemann@....com>, <wangqing@...o.com>,
        <robh+dt@...nel.org>, <rafael@...nel.org>,
        <ionela.voinescu@....com>, <pierre.gondois@....com>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-riscv@...ts.infradead.org>, <gshan@...hat.com>,
        <Valentina.FernandezAlanis@...rochip.com>
Subject: Re: [PATCH v5 09/19] arch_topology: Use the last level cache
 information from the cacheinfo

On 29/06/2022 18:49, Conor.Dooley@...rochip.com wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 27/06/2022 17:50, Sudeep Holla wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> The cacheinfo is now initialised early along with the CPU topology
>> initialisation. Instead of relying on the LLC ID information parsed
>> separately only with ACPI PPTT elsewhere, migrate to use the similar
>> information from the cacheinfo.
>>
>> This is generic for both DT and ACPI systems. The ACPI LLC ID information
>> parsed separately can now be removed from arch specific code.
> 
> Hey Sudeep,
> I bisected broken boot on PolarFire SoC to this patch in next-20220629 :/
> I suspect the issue is a missing "next-level-cache" in the the dt:
> arch/riscv/boot/dts/microchip/mpfs.dtsi
> 
> Adding next-level-cache = <&cctrllr> fixes the boot.

No, no it doesn't. Not sure what I was thinking there.
Prob tested that on the the last commit that bisect tested
rather than the one it pointed out the problem was with.

Either way, boot is broken in -next.

> Not sure what the resolution here is, old devicetrees are meant to keep
> booting, right?
> 
> Thanks,
> Conor.
> 
>>
>> Link: https://lore.kernel.org/r/20220621192034.3332546-10-sudeep.holla@arm.com
> 
> btw, why is this link in the patch? Why is a link to v4 relevant?
> Links to both v4 and v5 exist in your for-linux-next branch.
> 
> Log:
> git bisect start
> # bad: [c4ef528bd006febc7de444d9775b28706d924f78] Add linux-next specific files for 20220629
> git bisect bad c4ef528bd006febc7de444d9775b28706d924f78
> # good: [b13baccc3850ca8b8cccbf8ed9912dbaa0fdf7f3] Linux 5.19-rc2
> git bisect good b13baccc3850ca8b8cccbf8ed9912dbaa0fdf7f3
> # bad: [95c758a8899c4e8825a35a62a6f31667991217f9] Merge branch 'drm-next' of git://git.freedesktop.org/git/drm/drm.git
> git bisect bad 95c758a8899c4e8825a35a62a6f31667991217f9
> # bad: [5cbb9aeefe0070b627cd5c5528e6e63701561d57] Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux.git
> git bisect bad 5cbb9aeefe0070b627cd5c5528e6e63701561d57
> # good: [2e6556bae3e453cf27f3fb9c6144080e2a61707e] Merge branch 'libnvdimm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm.git
> git bisect good 2e6556bae3e453cf27f3fb9c6144080e2a61707e
> # good: [17efe76af33f6af09a821acce2e2e4e84819d381] Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git
> git bisect good 17efe76af33f6af09a821acce2e2e4e84819d381
> # good: [5aeeaf40d31288e8efa6ff2cbd952b13de077aa9] Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
> git bisect good 5aeeaf40d31288e8efa6ff2cbd952b13de077aa9
> # bad: [f64dfa36b325d107d8aca9727410343bd86d37dc] Merge branch 'stm32-next' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git
> git bisect bad f64dfa36b325d107d8aca9727410343bd86d37dc
> # good: [89459a2aef8832f044c8fbbec54b46cec05156c8] Merge branch 'next/dt' into for-next
> git bisect good 89459a2aef8832f044c8fbbec54b46cec05156c8
> # bad: [24cdefc96973ff1a1f6702470ad91ab019e5fedd] Merge branch 'arch_topology' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into for-linux-next
> git bisect bad 24cdefc96973ff1a1f6702470ad91ab019e5fedd
> # bad: [0d71f236f0a1067aba7660d056a9061b5877bf52] arch_topology: Avoid parsing through all the CPUs once a outlier CPU is found
> git bisect bad 0d71f236f0a1067aba7660d056a9061b5877bf52
> # good: [be6ab2e822888b8d9983d670fdabc09d753fd24f] cacheinfo: Use cache identifiers to check if the caches are shared if available
> git bisect good be6ab2e822888b8d9983d670fdabc09d753fd24f
> # bad: [854a3115f9ec0b889015c6854fbc0c1d69a46e4a] arm64: topology: Remove redundant setting of llc_id in CPU topology
> git bisect bad 854a3115f9ec0b889015c6854fbc0c1d69a46e4a
> # bad: [3b23bb2573e65b11be8f4b89023296dee7f06c0b] arch_topology: Use the last level cache information from the cacheinfo
> git bisect bad 3b23bb2573e65b11be8f4b89023296dee7f06c0b
> # good: [2f7b757eb69df296554bd39b0b2b2f4da678c736] arch_topology: Add support to parse and detect cache attributes
> git bisect good 2f7b757eb69df296554bd39b0b2b2f4da678c736
> # first bad commit: [3b23bb2573e65b11be8f4b89023296dee7f06c0b] arch_topology: Use the last level cache information from the cacheinfo
> 
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