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Message-ID: <f1f4a30e-7a84-30e2-197c-4153b3e66b64@microchip.com>
Date: Wed, 29 Jun 2022 19:39:43 +0000
From: <Conor.Dooley@...rochip.com>
To: <sudeep.holla@....com>
CC: <linux-kernel@...r.kernel.org>, <gregkh@...uxfoundation.org>,
<atishp@...shpatra.org>, <atishp@...osinc.com>,
<vincent.guittot@...aro.org>, <dietmar.eggemann@....com>,
<wangqing@...o.com>, <robh+dt@...nel.org>, <rafael@...nel.org>,
<ionela.voinescu@....com>, <pierre.gondois@....com>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-riscv@...ts.infradead.org>, <gshan@...hat.com>,
<Valentina.FernandezAlanis@...rochip.com>
Subject: Re: [PATCH v5 09/19] arch_topology: Use the last level cache
information from the cacheinfo
On 29/06/2022 19:42, Sudeep Holla wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Wed, Jun 29, 2022 at 06:18:25PM +0000, Conor.Dooley@...rochip.com wrote:
>>
>> No, no it doesn't. Not sure what I was thinking there.
>> Prob tested that on the the last commit that bisect tested
>> rather than the one it pointed out the problem was with.
>>
>> Either way, boot is broken in -next.
>>
>
> Can you check if the below fixes the issue?
Unfortunately, no joy.
Applied to a HEAD of 3b23bb2573e6 ("arch_topology: Use the
last level cache information from the cacheinfo").
Thanks,
Conor.
> Assuming presenting L1 as
> LLC might be causing issue.
>
> Regards,
> Sudeep
>
> -->8
> diff --git i/drivers/base/cacheinfo.c w/drivers/base/cacheinfo.c
> index 167abfa6f37d..a691317f7fdd 100644
> --- i/drivers/base/cacheinfo.c
> +++ w/drivers/base/cacheinfo.c
> @@ -60,7 +60,8 @@ bool last_level_cache_is_valid(unsigned int cpu)
>
> llc = per_cpu_cacheinfo_idx(cpu, cache_leaves(cpu) - 1);
>
> - return (llc->attributes & CACHE_ID) || !!llc->fw_token;
> + return (llc->type == CACHE_TYPE_UNIFIED) &&
> + ((llc->attributes & CACHE_ID) || !!llc->fw_token);
>
> }
>
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