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Date: Wed, 29 Jun 2022 08:35:32 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Vidya Sagar <vidyas@...dia.com>, bhelgaas@...gle.com,
lorenzo.pieralisi@....com, robh+dt@...nel.org,
thierry.reding@...il.com, jonathanh@...dia.com
Cc: kishon@...com, vkoul@...nel.org, kw@...ux.com,
p.zabel@...gutronix.de, mperttunen@...dia.com,
linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-phy@...ts.infradead.org, kthota@...dia.com,
mmaddireddy@...dia.com, sagar.tv@...il.com
Subject: Re: [PATCH V3 06/11] arm64: tegra: Add P2U and PCIe controller nodes
to Tegra234 DT
On 29/06/2022 08:04, Vidya Sagar wrote:
> Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree.
> The Tegra234 SoC contains 10 PCIe controllers and 24 P2U instances
> grouped into three different PHY bricks namely High-Speed IO (HSIO-8 P2Us)
> NVIDIA High Speed (NVHS-8 P2Us) and Gigabit Ethernet (GBE-8 P2Us)
> respectively.
>
> Signed-off-by: Vidya Sagar <vidyas@...dia.com>
> ---
> V3:
> * Added entries for all controllers that can operate in EndPoint mode
>
> V2:
> * Added 'iommu-map', 'iommu-map-mask' and 'dma-coherent' entries for each
> PCIe controller node
>
> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 935 +++++++++++++++++++++++
> 1 file changed, 935 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> index 2ae2f11f289c..062417e3ede5 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> @@ -998,6 +998,198 @@
> status = "okay";
> };
>
> + p2u_hsio_0: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03e00000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_1: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03e10000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_2: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03e20000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_3: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03e30000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_4: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03e40000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_5: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03e50000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_6: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03e60000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_hsio_7: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03e70000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_0: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03e90000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_1: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03ea0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_2: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03eb0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_3: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03ec0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_4: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03ed0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_5: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03ee0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_6: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03ef0000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_nvhs_7: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03f00000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_gbe_0: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03f20000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_gbe_1: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03f30000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_gbe_2: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03f40000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_gbe_3: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03f50000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_gbe_4: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03f60000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_gbe_5: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03f70000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_gbe_6: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03f80000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> + p2u_gbe_7: phy@...0000 {
> + compatible = "nvidia,tegra234-p2u";
> + reg = <0x03f90000 0x10000>;
> + reg-names = "ctl";
> +
> + #phy-cells = <0>;
> + };
> +
> hsp_aon: hsp@...0000 {
> compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
> reg = <0x0c150000 0x90000>;
> @@ -1384,6 +1576,749 @@
> status = "okay";
> };
>
> + pcie@...a0000 {
> + compatible = "nvidia,tegra234-pcie";
> + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>;
> + reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */
> + <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
> + <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
> + <0x00 0x2a080000 0x0 0x00040000>; /* DBI reg space (256K) */
> + reg-names = "appl", "config", "atu_dma", "dbi";
> +
> + status = "disabled";
Status goes to the end, not somewhere in the middle of properties.
Best regards,
Krzysztof
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