linux-kernel - Re: [PATCH 4/4] riscv: implement cache-management errata for T-Head SoCs

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Message-ID: <3ea5c3a7-8b17-18d5-9f38-bc0dcd79497d@sholland.org>
Date:   Tue, 28 Jun 2022 20:29:46 -0500
From:   Samuel Holland <samuel@...lland.org>
To:     Heiko Stuebner <heiko@...ech.de>
Cc:     palmer@...belt.com, paul.walmsley@...ive.com,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
        wefu@...hat.com, guoren@...nel.org, cmuellner@...ux.com,
        philipp.tomsich@...ll.eu, hch@....de, atishp@...shpatra.org,
        anup@...infault.org, mick@....forth.gr, robh+dt@...nel.org,
        krzk+dt@...nel.org, devicetree@...r.kernel.org,
        drew@...gleboard.org, rdunlap@...radead.org
Subject: Re: [PATCH 4/4] riscv: implement cache-management errata for T-Head
 SoCs

On 6/19/22 3:32 PM, Heiko Stuebner wrote:
> The T-Head C906 and C910 implement a scheme for handling
> cache operations different from the generic Zicbom extension.
> 
> Add an errata for it next to the generic dma coherency ops.
> 
> Signed-off-by: Heiko Stuebner <heiko@...ech.de>

Thanks for the update!

Reviewed-by: Samuel Holland <samuel@...lland.org>
Tested-by: Samuel Holland <samuel@...lland.org>