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Message-ID: <20220629134147.GA16868@duo.ucw.cz>
Date: Wed, 29 Jun 2022 15:41:47 +0200
From: Pavel Machek <pavel@....cz>
To: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
Cc: Marc Zyngier <maz@...nel.org>,
Geert Uytterhoeven <geert@...ux-m68k.org>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
Thomas Gleixner <tglx@...utronix.de>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Sagar Kadam <sagar.kadam@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
linux-riscv <linux-riscv@...ts.infradead.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
LKML <linux-kernel@...r.kernel.org>,
Biju Das <biju.das.jz@...renesas.com>
Subject: Re: [PATCH v2 2/2] irqchip/sifive-plic: Add support for Renesas
RZ/Five SoC
Hi!
> > >> +#define PLIC_QUIRK_EDGE_INTERRUPT BIT(0)
> > >>
> > >> struct plic_priv {
> > >> struct cpumask lmask;
> > >> struct irq_domain *irqdomain;
> > >> void __iomem *regs;
> > >> + u32 plic_quirks;
> > >> };
> > >>
> > >> What about something like above?
> > >
> > > LGTM.
> > >
> > > Marc suggested to make this unsigned long, but TBH, that won't make
> > > much of a difference. PLICs are present on RV32 SoCs, too, so you
> > > cannot rely on having more than 32 bits anyway.
> >
> > But it will make a difference on a 64bit platform, as we want to
> > use test_bit() and co to check for features.
> >
> Ok will change that to unsigned long and use the test_bit/set_bit instead.
Is there good enough reason for that? test_bit/... are when you need
atomicity, and that's not the case here. Plain old & ... should be
enough.
Best regards,
Pavel
--
People of Russia, stop Putin before his war on Ukraine escalates.
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