linux-kernel - Re: [PATCH] riscv: dts: microchip: hook up the mpfs' l2cache

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Message-ID: <20220630154132.i54to4l4divkbr2d@bogus>
Date:   Thu, 30 Jun 2022 16:41:32 +0100
From:   Sudeep Holla <sudeep.holla@....com>
To:     Conor Dooley <conor@...nel.org>
Cc:     Daire McNamara <daire.mcnamara@...rochip.com>,
        Ivan Griffin <ivan.griffin@...rochip.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Palmer Dabbelt <palmer@...osinc.com>,
        linux-riscv@...ts.infradead.org,
        Conor Dooley <conor.dooley@...rochip.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Atish Patra <atishp@...shpatra.org>,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] riscv: dts: microchip: hook up the mpfs' l2cache

On Wed, Jun 29, 2022 at 09:07:33PM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@...rochip.com>
> 
> The initial PolarFire SoC devicetree must have been forked off from
> the fu540 one prior to the addition of l2cache controller support being
> added there. When the controller node was added to mpfs.dtsi, it was
> not hooked up to the CPUs & thus sysfs reports an incorrect cache
> configuration. Hook it up.
>

Reviewed-by: Sudeep Holla <sudeep.holla@....com>

-- 
Regards,
Sudeep