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Message-ID: <HK0PR06MB3202B894962013238CB93B2880BA9@HK0PR06MB3202.apcprd06.prod.outlook.com>
Date: Thu, 30 Jun 2022 03:17:05 +0000
From: Neal Liu <neal_liu@...eedtech.com>
To: Dhananjay Phadke <dphadke@...ux.microsoft.com>,
Corentin Labbe <clabbe.montjoie@...il.com>,
Christophe JAILLET <christophe.jaillet@...adoo.fr>,
Randy Dunlap <rdunlap@...radead.org>,
Herbert Xu <herbert@...dor.apana.org.au>,
"David S . Miller" <davem@...emloft.net>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Joel Stanley <joel@....id.au>,
Andrew Jeffery <andrew@...id.au>,
Dhananjay Phadke <dhphadke@...rosoft.com>,
Johnny Huang <johnny_huang@...eedtech.com>
CC: "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-aspeed@...ts.ozlabs.org" <linux-aspeed@...ts.ozlabs.org>,
BMC-SW <BMC-SW@...eedtech.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-crypto@...r.kernel.org" <linux-crypto@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>
Subject: RE: [PATCH v6 2/5] dt-bindings: clock: Add AST2500/AST2600 HACE reset
definition
> -----Original Message-----
> From: Dhananjay Phadke <dphadke@...ux.microsoft.com>
> Sent: Wednesday, June 29, 2022 7:50 PM
> To: Neal Liu <neal_liu@...eedtech.com>; Corentin Labbe
> <clabbe.montjoie@...il.com>; Christophe JAILLET
> <christophe.jaillet@...adoo.fr>; Randy Dunlap <rdunlap@...radead.org>;
> Herbert Xu <herbert@...dor.apana.org.au>; David S . Miller
> <davem@...emloft.net>; Rob Herring <robh+dt@...nel.org>; Krzysztof
> Kozlowski <krzysztof.kozlowski+dt@...aro.org>; Joel Stanley <joel@....id.au>;
> Andrew Jeffery <andrew@...id.au>; Dhananjay Phadke
> <dhphadke@...rosoft.com>; Johnny Huang
> <johnny_huang@...eedtech.com>
> Cc: devicetree@...r.kernel.org; linux-aspeed@...ts.ozlabs.org; BMC-SW
> <BMC-SW@...eedtech.com>; linux-kernel@...r.kernel.org;
> linux-crypto@...r.kernel.org; linux-arm-kernel@...ts.infradead.org
> Subject: Re: [PATCH v6 2/5] dt-bindings: clock: Add AST2500/AST2600 HACE
> reset definition
>
> On 6/29/2022 2:44 AM, Neal Liu wrote:
> > Add HACE reset bit definition for AST2500/AST2600.
> >
> > Signed-off-by: Neal Liu <neal_liu@...eedtech.com>
> > Signed-off-by: Johnny Huang <johnny_huang@...eedtech.com>
> > ---
> > include/dt-bindings/clock/aspeed-clock.h | 1 +
> > include/dt-bindings/clock/ast2600-clock.h | 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/include/dt-bindings/clock/aspeed-clock.h
> > b/include/dt-bindings/clock/aspeed-clock.h
> > index 9ff4f6e4558c..06d568382c77 100644
> > --- a/include/dt-bindings/clock/aspeed-clock.h
> > +++ b/include/dt-bindings/clock/aspeed-clock.h
> > @@ -52,5 +52,6 @@
> > #define ASPEED_RESET_I2C 7
> > #define ASPEED_RESET_AHB 8
> > #define ASPEED_RESET_CRT1 9
> > +#define ASPEED_RESET_HACE 10
>
> NAK.
>
> I replied to older v5 of this patch, but this v6 also looks incorrect as per HW
> manual.
>
> https://lore.kernel.org/linux-arm-kernel/20220629032008.1579899-1-neal_liu
> @aspeedtech.com/T/#m000bd3388b3e41117aa0eef10bf6f8a6a3a85cce
>
> For both AST2400 and AST2500:
> SCU04[10] = PECI.
>
> It will be best to refactor/split aspeed-clock.h into separate files.
Hi, based on @Krzysztof mentioned, change these define is not allowed due to breaking ABI.
So another way is to define a new value(interface), and we can change driver's implementation.
I know this is not intuitive to hardware register's value, it also confused me at the first time.
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