lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Thu, 30 Jun 2022 10:38:46 +0100
From:   Jon Hunter <jonathanh@...dia.com>
To:     Kartik <kkartik@...dia.com>, daniel.lezcano@...aro.org,
        tglx@...utronix.de, robh+dt@...nel.org, krzk+dt@...nel.org,
        thierry.reding@...il.com, spujar@...dia.com,
        akhilrajeev@...dia.com, rgumasta@...dia.com, pshete@...dia.com,
        vidyas@...dia.com, mperttunen@...dia.com, mkumard@...dia.com,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        linux-tegra@...r.kernel.org
Subject: Re: [PATCH v2 5/6] arm64: tegra: Enable native timers on Tegra194


On 29/06/2022 19:29, Kartik wrote:
> From: Thierry Reding <treding@...dia.com>
> 
> The native timers IP block found on NVIDIA Tegra SoCs implements a
> watchdog timer that can be used to recover from system hangs. Add and
> enable the device tree node on Tegra194.
> 
> Signed-off-by: Thierry Reding <treding@...dia.com>
> Signed-off-by: Kartik <kkartik@...dia.com>
> ---
>   arch/arm64/boot/dts/nvidia/tegra194.dtsi | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index 9566c6388ed9..4b37aec69448 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -698,6 +698,22 @@
>   			};
>   		};
>   
> +		timer@...0000 {
> +			compatible = "nvidia,tegra186-timer";
> +			reg = <0x03010000 0x000e0000>;
> +			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "okay";
> +		};
> +
>   		uarta: serial@...0000 {
>   			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
>   			reg = <0x03100000 0x40>;


Reviewed-by: Jon Hunter <jonathanh@...dia.com>

Thanks!
Jon

-- 
nvpublic

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ