linux-kernel - Re: [PATCH v2 2/8] dt-bindings: mtd: intel: lgm-nand: Fix maximum chip select value

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Message-ID: <20220701194857.GA1403235-robh@kernel.org>
Date:   Fri, 1 Jul 2022 13:48:57 -0600
From:   Rob Herring <robh@...nel.org>
To:     Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Cc:     miquel.raynal@...tlin.com, rtanwar@...linear.com, vigneshr@...com,
        tlanger@...linear.com, devicetree@...r.kernel.org, richard@....at,
        linux-kernel@...r.kernel.org, linux-mtd@...ts.infradead.org
Subject: Re: [PATCH v2 2/8] dt-bindings: mtd: intel: lgm-nand: Fix maximum
 chip select value

On Wed, 29 Jun 2022 23:35:02 +0200, Martin Blumenstingl wrote:
> The Intel LGM NAND IP only supports two chip selects: There's only two
> CS and ADDR_SEL register sets. Fix the maximum allowed chip select value
> according to the dt-bindings.
> 
> Fixes: 2f9cea8eae44f5 ("dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
> ---
>  Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@...nel.org>