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Message-ID: <87mtdseh6u.wl-maz@kernel.org>
Date: Fri, 01 Jul 2022 21:00:57 +0100
From: Marc Zyngier <maz@...nel.org>
To: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
Thomas Gleixner <tglx@...utronix.de>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Linus Walleij <linus.walleij@...aro.org>,
Bartosz Golaszewski <brgl@...ev.pl>,
Philipp Zabel <p.zabel@...gutronix.de>,
"open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>, LKML <linux-kernel@...r.kernel.org>,
Biju Das <biju.das.jz@...renesas.com>
Subject: Re: [PATCH v6 5/5] pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt
On Fri, 01 Jul 2022 19:15:41 +0100,
"Lad, Prabhakar" <prabhakar.csengg@...il.com> wrote:
>
> Hi Marc,
>
> On Wed, Jun 29, 2022 at 5:26 PM Marc Zyngier <maz@...nel.org> wrote:
> >
> > On Sat, 25 Jun 2022 21:06:00 +0100,
> > Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com> wrote:
> > >
> > > Add IRQ domain to RZ/G2L pinctrl driver to handle GPIO interrupt.
> > >
> > > GPIO0-GPIO122 pins can be used as IRQ lines but only 32 pins can be
> > > used as IRQ lines at a given time. Selection of pins as IRQ lines
> > > is handled by IA55 (which is the IRQC block) which sits in between the
> > > GPIO and GIC.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > > ---
> > > drivers/pinctrl/renesas/pinctrl-rzg2l.c | 236 ++++++++++++++++++++++++
> > > 1 file changed, 236 insertions(+)
> > >
> >
> > [...]
> >
> > > +static void *rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip,
> > > + unsigned int parent_hwirq,
> > > + unsigned int parent_type)
> > > +{
> > > + struct irq_fwspec *fwspec;
> > > +
> > > + fwspec = kzalloc(sizeof(*fwspec), GFP_KERNEL);
> > > + if (!fwspec)
> > > + return NULL;
> > > +
> > > + fwspec->fwnode = chip->irq.parent_domain->fwnode;
> > > + fwspec->param_count = 2;
> > > + fwspec->param[0] = parent_hwirq;
> > > + fwspec->param[1] = parent_type;
> > > +
> > > + return fwspec;
> > > +}
> >
> > I jumped at this one again.
> >
> > Can you please pick [1] as part of your series and write this in a way
> > that doesn't require extra memory allocation? It has already been
> > ack'ed by Linus anyway, and we'd put an end to this thing for good.
> >
> > Thanks,
> >
> > M.
> >
> > [1] https://lore.kernel.org/r/20220512162320.2213488-1-maz@kernel.org
> >
> I tried applying [1] on linux-next (c4185b16aba7) and 5.19-rc4
> (03c765b0e3b4) but this patch does not apply cleanly. Can you please
> point me to the repo where this patch exists (or repo where the patch
> applies cleanly)?
Odd, it applies cleanly here to -rc4. Anyway, I've now pushed it out
to [1] with Linus' RB and a typo fix in the commit message.
Thanks,
M.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/log/?h=irq/gpio-fwspec-stack
--
Without deviation from the norm, progress is not possible.
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