linux-kernel - Re: [PATCH v12 net-next 2/9] net: mdio: mscc-miim: add ability to be used in a non-mmio configuration

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20220701203830.GC3327062@euler>
Date:   Fri, 1 Jul 2022 13:38:30 -0700
From:   Colin Foster <colin.foster@...advantage.com>
To:     Andy Shevchenko <andy.shevchenko@...il.com>
Cc:     devicetree <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        netdev <netdev@...r.kernel.org>,
        linux-arm Mailing List <linux-arm-kernel@...ts.infradead.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        Vladimir Oltean <vladimir.oltean@....com>,
        Lee Jones <lee.jones@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Andrew Lunn <andrew@...n.ch>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Russell King <linux@...linux.org.uk>,
        "David S. Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>,
        Lars Povlsen <lars.povlsen@...rochip.com>,
        Steen Hegelund <Steen.Hegelund@...rochip.com>,
        Microchip Linux Driver Support <UNGLinuxDriver@...rochip.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        Wolfram Sang <wsa@...nel.org>,
        Terry Bowman <terry.bowman@....com>,
        katie.morris@...advantage.com
Subject: Re: [PATCH v12 net-next 2/9] net: mdio: mscc-miim: add ability to be
 used in a non-mmio configuration

On Fri, Jul 01, 2022 at 10:24:46PM +0200, Andy Shevchenko wrote:
> On Fri, Jul 1, 2022 at 9:26 PM Colin Foster
> <colin.foster@...advantage.com> wrote:
> >
> > There are a few Ocelot chips that contain the logic for this bus, but are
> > controlled externally. Specifically the VSC7511, 7512, 7513, and 7514. In
> > the externally controlled configurations these registers are not
> > memory-mapped.
> >
> > Add support for these non-memory-mapped configurations.
> 
> ...
> 
> > +       phy_regmap = ocelot_regmap_from_resource_optional(pdev, 1,
> > +                                                &mscc_miim_phy_regmap_config);
> > +       if (IS_ERR(phy_regmap)) {
> > +               dev_err(dev, "Unable to create phy register regmap\n");
> > +               return PTR_ERR(phy_regmap);
> 
> return dev_err_probe(...); ?

Thanks. Also the same is in pinctrl-ocelot. Fixing in my tree right now.

> 
> >         }
> 
> -- 
> With Best Regards,
> Andy Shevchenko