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Message-ID: <CAGETcx-ToG1xAtKVuZqwQK7hvVbT+Q0J0m4oWVCtR55XiYqETQ@mail.gmail.com>
Date:   Fri, 1 Jul 2022 15:28:58 -0700
From:   Saravana Kannan <saravanak@...gle.com>
To:     Mark Brown <broonie@...nel.org>
Cc:     Geert Uytterhoeven <geert+renesas@...der.be>,
        Ulf Hansson <ulf.hansson@...aro.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        kernelci-results@...ups.io, bot@...nelci.org,
        gtucker@...labora.com, Michael Walle <michael@...le.cc>,
        linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: next/master bisection: baseline.bootrr.imx6q-pcie-pcie0-probed on kontron-pitx-imx8m

On Fri, Jul 1, 2022 at 2:16 AM Mark Brown <broonie@...nel.org> wrote:
>
> On Thu, Jun 30, 2022 at 06:02:04PM -0700, Saravana Kannan wrote:
>
> > The patch attached to that email will probably fix this issue. I
> > haven't dealt with Kernel CI bot before. Is there a way to get it to
> > test a patch?
>
> It is but I don't have access to do that - either the lab owner
> (Michael, CCed here) or Guillaume (also CCed) should be able to help
> there.

I found a much simpler solution that I think should work. Snippet at
the end of this email.
https://lore.kernel.org/lkml/CAGETcx-fLAXnG+1S4MHJwg9t7O6jj6Mp+q25bh==C_Z1CLs-mg@mail.gmail.com/

I'm waiting for Alexander in that thread to give it a shot.

Michael/Guillaume, if you want to give it a shot too, that'll be nice :)

Thanks,
Saravana

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