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Message-ID: <198fc303-30e5-31c7-5159-b787916ee6d8@somainline.org>
Date: Fri, 1 Jul 2022 09:31:17 +0200
From: Konrad Dybcio <konrad.dybcio@...ainline.org>
To: Sricharan Ramabadhran <quic_srichara@...cinc.com>,
agross@...nel.org, bjorn.andersson@...aro.org, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, mturquette@...libre.com,
sboyd@...nel.org, linus.walleij@...aro.org,
catalin.marinas@....com, p.zabel@...gutronix.de,
quic_varada@...cinc.com, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, linux-gpio@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH V2 7/8] arm64: dts: Add ipq5018 SoC and MP03 board support
On 28.06.2022 09:14, Sricharan Ramabadhran wrote:
> Thanks Konrad for the review.
>
> On 6/27/2022 12:02 AM, Konrad Dybcio wrote:
>>
>> On 21.06.2022 18:11, Sricharan R wrote:
>>> From: Varadarajan Narayanan <quic_varada@...cinc.com>
>>>
>>> Add initial device tree support for the Qualcomm IPQ5018 SoC and
>>> MP03.1-C2 board.
>>>
>>> Co-developed-by: Sricharan R <quic_srichara@...cinc.com>
>>> Signed-off-by: Sricharan R <quic_srichara@...cinc.com>
>>> Signed-off-by: Varadarajan Narayanan <quic_varada@...cinc.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>>> .../arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts | 29 +++
>>> arch/arm64/boot/dts/qcom/ipq5018.dtsi | 221 ++++++++++++++++++
>>> 3 files changed, 251 insertions(+)
>>> create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
>>> create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>>> index f9e6343acd03..c44e701f093c 100644
>>> --- a/arch/arm64/boot/dts/qcom/Makefile
>>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>>> @@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c2.dtb
>>> dtb-$(CONFIG_ARCH_QCOM) += msm8916-alcatel-idol347.dtb
>>> dtb-$(CONFIG_ARCH_QCOM) += msm8916-asus-z00l.dtb
>>> dtb-$(CONFIG_ARCH_QCOM) += msm8916-huawei-g7.dtb
>>> +dtb-$(CONFIG_ARCH_QCOM) += ipq5018-mp03.1-c2.dtb
>>> dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8150.dtb
>>> dtb-$(CONFIG_ARCH_QCOM) += msm8916-longcheer-l8910.dtb
>>> dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
>>> new file mode 100644
>>> index 000000000000..d1cd080ec3db
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
>>> @@ -0,0 +1,29 @@
>>> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
>>> +/*
>>> + * IPQ5018 CP01 board device tree source
>>> + *
>>> + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
>>> + */
>>> +
>>> +/dts-v1/;
>>> +
>>> +#include "ipq5018.dtsi"
>>> +
>>> +/ {
>>> + model = "Qualcomm Technologies, Inc. IPQ5018/AP-MP03-C2";
>>> + compatible = "qcom,ipq5018-mp03", "qcom,ipq5018";
>>> +
>>> + aliases {
>>> + serial0 = &blsp1_uart1;
>>> + };
>>> +
>>> + chosen {
>>> + stdout-path = "serial0:115200n8";
>>> + };
>>> +};
>>> +
>>> +&blsp1_uart1 {
>>> + pinctrl-0 = <&serial_1_pins>;
>>> + pinctrl-names = "default";
>>> + status = "ok";
>>> +};
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>>> new file mode 100644
>>> index 000000000000..084fb7b30dfd
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
>>> @@ -0,0 +1,221 @@
>>> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
>>> +/*
>>> + * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
>>> + */
>>> +/*
>>> + * IPQ5018 SoC device tree source
>>> + *
>>> + * Copyright (c) 2019, The Linux Foundation. All rights reserved.
>>> + */
>>> +
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
>>> +#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
>>> +
>>> +/ {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + interrupt-parent = <&intc>;
>> Hi!
>>
>> interrupt-parent could go first.
>
> ok.
>
>
>>> +
>>> + sleep_clk: sleep-clk {
>>> + compatible = "fixed-clock";
>>> + clock-frequency = <32000>;
>>> + #clock-cells = <0>;
>>> + };
>>> +
>>> + xo: xo {
>>> + compatible = "fixed-clock";
>>> + clock-frequency = <24000000>;
>>> + #clock-cells = <0>;
>>> + };
>>> +
>>> + gen2clk0: gen2clk0 {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <125000000>;
>>> + clock-output-names = "pcie20_phy0_pipe_clk";
>>> + };
>>> +
>>> + gen2clk1: gen2clk1 {
>>> + compatible = "fixed-clock";
>>> + #clock-cells = <0>;
>>> + clock-frequency = <125000000>;
>>> + clock-output-names = "pcie20_phy1_pipe_clk";
>>> + };
>> I am not sure what's the current stance on this, but previously clock nodes
>> used to be wrapped in a clocks {} node, as currently they are not sorted
>> properly.
>>
> hmm ok, yeah, see the clocks { node in some recent dts as well, will add the wrapper.
>
>
>>> +
>>> + cpus: cpus {
>> Is this label going to be used?
> hmm, not used, will remove.
>>> + #address-cells = <1>;
>>> + #size-cells = <0>;
>>> +
>>> + CPU0: cpu@0 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a53";
>>> + reg = <0x0>;
>>> + enable-method = "psci";
>>> + next-level-cache = <&L2_0>;
>>> + };
>>> +
>>> + CPU1: cpu@1 {
>>> + device_type = "cpu";
>>> + compatible = "arm,cortex-a53";
>>> + enable-method = "psci";
>>> + reg = <0x1>;
>>> + next-level-cache = <&L2_0>;
>>> + };
>>> +
>>> + L2_0: l2-cache {
>>> + compatible = "cache";
>>> + cache-level = <0x2>;
>> This should probably be dec, as it's not a register.
>
> 'dec' ? Sorry, i did not get that.
Short for decimal.
Konrad
[snip]
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