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Message-Id: <31b74e43d3af263e1b943bca1dd3debe885521d8.1656660185.git.viresh.kumar@linaro.org>
Date: Fri, 1 Jul 2022 13:50:09 +0530
From: Viresh Kumar <viresh.kumar@...aro.org>
To: Rob Clark <robdclark@...il.com>,
Abhinav Kumar <quic_abhinavk@...cinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
Sean Paul <sean@...rly.run>
Cc: Viresh Kumar <viresh.kumar@...aro.org>, linux-pm@...r.kernel.org,
Vincent Guittot <vincent.guittot@...aro.org>,
"Rafael J. Wysocki" <rafael@...nel.org>,
Stephen Boyd <sboyd@...nel.org>, Nishanth Menon <nm@...com>,
linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org
Subject: [PATCH V2 14/30] drm/msm: Migrate to dev_pm_opp_set_config()
The OPP core now provides a unified API for setting all configuration
types, i.e. dev_pm_opp_set_config().
Lets start using it.
Signed-off-by: Viresh Kumar <viresh.kumar@...aro.org>
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 8 ++++++--
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 10 +++++-----
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 +++++-
drivers/gpu/drm/msm/dp/dp_ctrl.c | 6 +++++-
drivers/gpu/drm/msm/dsi/dsi_host.c | 6 +++++-
5 files changed, 26 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index c424e9a37669..6ebb5a28c501 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -1723,10 +1723,14 @@ static void check_speed_bin(struct device *dev)
{
struct nvmem_cell *cell;
u32 val;
+ struct dev_pm_opp_config config = {
+ .supported_hw = &val,
+ .supported_hw_count = 1,
+ };
/*
* If the OPP table specifies a opp-supported-hw property then we have
- * to set something with dev_pm_opp_set_supported_hw() or the table
+ * to set something with dev_pm_opp_set_config() or the table
* doesn't get populated so pick an arbitrary value that should
* ensure the default frequencies are selected but not conflict with any
* actual bins
@@ -1748,7 +1752,7 @@ static void check_speed_bin(struct device *dev)
nvmem_cell_put(cell);
}
- devm_pm_opp_set_supported_hw(dev, &val, 1);
+ devm_pm_opp_set_config(dev, &config);
}
struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 42ed9a3c4905..82801311f7d4 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1800,6 +1800,10 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev)
u32 supp_hw = UINT_MAX;
u32 speedbin;
int ret;
+ struct dev_pm_opp_config config = {
+ .supported_hw = &supp_hw,
+ .supported_hw_count = 1,
+ };
ret = adreno_read_speedbin(dev, &speedbin);
/*
@@ -1818,11 +1822,7 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev)
supp_hw = fuse_to_supp_hw(dev, rev, speedbin);
done:
- ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1);
- if (ret)
- return ret;
-
- return 0;
+ return devm_pm_opp_set_config(dev, &config);
}
static const struct adreno_gpu_funcs funcs = {
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index e23e2552e802..2213ce52d2fa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1215,12 +1215,16 @@ static int dpu_kms_init(struct drm_device *ddev)
struct dev_pm_opp *opp;
int ret = 0;
unsigned long max_freq = ULONG_MAX;
+ struct dev_pm_opp_config config = {
+ .clk_names = (const char *[]){ "core" },
+ .clk_count = 1,
+ };
dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL);
if (!dpu_kms)
return -ENOMEM;
- ret = devm_pm_opp_set_clkname(dev, "core");
+ ret = devm_pm_opp_set_config(dev, &config);
if (ret)
return ret;
/* OPP table is optional */
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index b7f5b8d3bbd6..0c8fc151b4be 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -2022,6 +2022,10 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
{
struct dp_ctrl_private *ctrl;
int ret;
+ struct dev_pm_opp_config config = {
+ .clk_names = (const char *[]){ "ctrl_link" },
+ .clk_count = 1,
+ };
if (!dev || !panel || !aux ||
!link || !catalog) {
@@ -2035,7 +2039,7 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
return ERR_PTR(-ENOMEM);
}
- ret = devm_pm_opp_set_clkname(dev, "ctrl_link");
+ ret = devm_pm_opp_set_config(dev, &config);
if (ret) {
dev_err(dev, "invalid DP OPP table in device tree\n");
/* caller do PTR_ERR(opp_table) */
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index a95d5df52653..35b6722d1cf9 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -2034,6 +2034,10 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi)
struct msm_dsi_host *msm_host = NULL;
struct platform_device *pdev = msm_dsi->pdev;
int ret;
+ struct dev_pm_opp_config config = {
+ .clk_names = (const char *[]){ "byte" },
+ .clk_count = 1,
+ };
msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
if (!msm_host) {
@@ -2095,7 +2099,7 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi)
goto fail;
}
- ret = devm_pm_opp_set_clkname(&pdev->dev, "byte");
+ ret = devm_pm_opp_set_config(&pdev->dev, &config);
if (ret)
return ret;
/* OPP table is optional */
--
2.31.1.272.g89b43f80a514
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