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Message-Id: <1656667961-1799-1-git-send-email-shengjiu.wang@nxp.com>
Date:   Fri,  1 Jul 2022 17:32:35 +0800
From:   Shengjiu Wang <shengjiu.wang@....com>
To:     nicoleotsuka@...il.com, Xiubo.Lee@...il.com, festevam@...il.com,
        shengjiu.wang@...il.com, lgirdwood@...il.com, broonie@...nel.org,
        perex@...ex.cz, tiwai@...e.com, alsa-devel@...a-project.org,
        robh+dt@...nel.org, krzk+dt@...nel.org, devicetree@...r.kernel.org
Cc:     linuxppc-dev@...ts.ozlabs.org, linux-kernel@...r.kernel.org
Subject: [PATCH v2 0/6] Add support of two Audio PLL source

i.MX8MQ/MN/MM/MP platforms typically have 2 AUDIO PLLs being
configured to handle 8kHz and 11kHz series audio rates.

The patches implement the functionality to select at runtime
the appropriate AUDIO PLL for root clock, if there is no
two PLL registered, then no action taken.

change in v2:
- simply the logic for calling reparent function

Shengjiu Wang (6):
  ASoC: fsl_utils: Add function to handle PLL clock source
  ASoC: fsl_spdif: Add support for PLL switch at runtime.
  ASoC: fsl_micfil: Add support for PLL switch at runtime
  ASoC: fsl_sai: Add support for PLL switch at runtime
  ASoC: dt-bindings: fsl_spdif: Add two PLL clock source
  ASoC: dt-bindings: fsl-sai: Add two PLL clock source

 .../devicetree/bindings/sound/fsl,spdif.yaml  |  4 ++
 .../devicetree/bindings/sound/fsl-sai.txt     |  3 +
 sound/soc/fsl/Kconfig                         |  3 +
 sound/soc/fsl/fsl_micfil.c                    | 31 +++++++++
 sound/soc/fsl/fsl_sai.c                       | 38 ++++++++++
 sound/soc/fsl/fsl_sai.h                       |  2 +
 sound/soc/fsl/fsl_spdif.c                     | 48 +++++++++++--
 sound/soc/fsl/fsl_utils.c                     | 69 +++++++++++++++++++
 sound/soc/fsl/fsl_utils.h                     |  7 ++
 9 files changed, 200 insertions(+), 5 deletions(-)

-- 
2.17.1

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