linux-kernel - [irqchip: irq/irqchip-next] dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC

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Date:   Fri, 01 Jul 2022 14:37:35 -0000
From:   "irqchip-bot for Samuel Holland" <tip-bot2@...utronix.de>
To:     linux-kernel@...r.kernel.org
Cc:     Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
        Samuel Holland <samuel@...lland.org>,
        Marc Zyngier <maz@...nel.org>, tglx@...utronix.de
Subject: [irqchip: irq/irqchip-next] dt-bindings: interrupt-controller:
 Require trigger type for T-HEAD PLIC

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID:     d60df7fd225af37e31859a9badb0cca73f7aa12d
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/d60df7fd225af37e31859a9badb0cca73f7aa12d
Author:        Samuel Holland <samuel@...lland.org>
AuthorDate:    Thu, 30 Jun 2022 05:02:40 -05:00
Committer:     Marc Zyngier <maz@...nel.org>
CommitterDate: Fri, 01 Jul 2022 15:27:23 +01:00

dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC

The RISC-V PLIC specification unfortunately allows PLIC implementations
to ignore edges seen while an edge-triggered interrupt is being handled:

  Depending on the design of the device and the interrupt handler,
  in between sending an interrupt request and receiving notice of its
  handler’s completion, the gateway might either ignore additional
  matching edges or increment a counter of pending interrupts.

Like the NCEPLIC100, the T-HEAD C900 PLIC also has this behavior. Thus
it also needs to inform software about each interrupt's trigger type, so
the driver can use the right interrupt flow.

Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Signed-off-by: Samuel Holland <samuel@...lland.org>
Signed-off-by: Marc Zyngier <maz@...nel.org>
Link: https://lore.kernel.org/r/20220630100241.35233-4-samuel@sholland.org
---
 Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index cd2b8bc..92e0f8c 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -33,7 +33,7 @@ description:
   it is not included in the interrupt specifier. In the second case, software
   needs to know the trigger type, so it can reorder the interrupt flow to avoid
   missing interrupts. This special handling is needed by at least the Renesas
-  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100).
+  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
 
   While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
   "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
@@ -112,6 +112,7 @@ allOf:
           contains:
             enum:
               - andestech,nceplic100
+              - thead,c900-plic
 
     then:
       properties: