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Date:   Mon, 4 Jul 2022 20:37:38 +0800
From:   Qi Hu <huqi@...ngson.cn>
To:     Xi Ruoyao <xry111@...111.site>, WANG Xuerui <kernel@...0n.name>,
        Huacai Chen <chenhuacai@...nel.org>,
        Jiaxun Yang <jiaxun.yang@...goat.com>
Cc:     loongarch@...ts.linux.dev, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] LoongArch: Clean useless vcsr in loongarch_fpu.


On 2022/7/4 17:58, Xi Ruoyao wrote:
> On Mon, 2022-07-04 at 17:27 +0800, huqi wrote:
>
>>> The original code was written with future LSX/LASX support in mind;
>>> the code is dead currently, but expected to get utilized Soon (TM).
>>>
>>> So, I'd like to confirm if future LoongArch models would *not* feature
>>> LSX/LASX in its current form, and that the Loongson Corporation is not
>>> going to upstream LSX/LASX support, given you are apparently a
>>> Loongson employee with the first-hand information? We'd like to avoid
>>> code churn in general, so if the LSX/LASX support is to be eventually
>>> mainlined, removing them now would only lead to them being introduced
>>> later.
>> `vcsr` is removed because it has been removed in hardware. What's more,
>> it will not be used to support LSX/LASX in the future.
> It would be better to add this information into the commit message.  Is
> it already removed in 3A5000?  On my machine "movfcsr2gr $a0, $r16"
> produces SIGILL (but maybe it's because LSX is not enabled via the EUEN
> register).

Yes, adding this information to the commit message will be more 
reasonable. I will do it later.

It is true that 3A5000 has removed this register. $r16 to $r31 are 
reserved for LSX/LASX. So "movfcsr2gr $a0, $r16" will raise SXD/ASXD if 
LSX/LASX is not enabled, and kernel will raise SIGILL.

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