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Message-ID: <7d5986ad-40a4-f15b-8d14-aad5248379b3@collabora.com>
Date: Tue, 5 Jul 2022 15:00:14 +0200
From: AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com>
To: Irui Wang <irui.wang@...iatek.com>,
Hans Verkuil <hverkuil-cisco@...all.nl>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Matthias Brugger <matthias.bgg@...il.com>,
Tzung-Bi Shih <tzungbi@...omium.org>,
nicolas.dufresne@...labora.com, wenst@...omium.org
Cc: Project_Global_Chrome_Upstream_Group@...iatek.com,
linux-media@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
Tomasz Figa <tfiga@...omium.org>, xia.jiang@...iatek.com,
maoguang.meng@...iatek.com, kyrie wu <kyrie.wu@...iatek.com>,
srv_heupstream@...iatek.com
Subject: Re: [V4,1/8] dt-bindings: mediatek: Add mediatek,mt8195-jpgdec
compatible
Il 27/06/22 04:55, Irui Wang ha scritto:
> From: kyrie wu <kyrie.wu@...iatek.com>
>
> Add mediatek,mt8195-jpgdec compatible to binding document.
>
> Signed-off-by: kyrie wu <kyrie.wu@...iatek.com>
> ---
> .../media/mediatek,mt8195-jpegdec.yaml | 176 ++++++++++++++++++
> 1 file changed, 176 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
> new file mode 100644
> index 000000000000..8a255e8e2e09
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml
> @@ -0,0 +1,176 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek,mt8195-jpegdec.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
...snip...
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/memory/mt8195-memory-port.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/clock/mt8195-clk.h>
> + #include <dt-bindings/power/mt8195-power.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + jpgdec_master {
Additionally to Rob's review, which I of course fully agree on, this example
devicetree does *not* work on MT8195.
[ 13.015716] mtk-jpegdec-hw 1a040000.jpgdec: Adding to iommu group 1
[ 13.025383] mtk-jpegdec-hw 1a050000.jpgdec: Adding to iommu group 1
[ 13.034814] mtk-jpegdec-hw 1b040000.jpgdec: Adding to iommu group 1
[ 13.041672] mtk-jpeg soc:jpgdec_master: invalid resource
[ 13.049758] mtk-jpeg: probe of soc:jpgdec_master failed with error -22
Regards,
Angelo
> + compatible = "mediatek,mt8195-jpgdec";
> + mediatek,jpegdec-multi-core;
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
> + iommus = <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA0>,
> + <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA0>,
> + <&iommu_vpp M4U_PORT_L19_JPGDEC_WDMA1>,
> + <&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>,
> + <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
> + <&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + jpgdec@...40000 {
> + compatible = "mediatek,mt8195-jpgdec-hw";
> + reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
> + hw_id = <0>;
> + iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
> + interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vencsys CLK_VENC_JPGDEC>;
> + clock-names = "jpgdec";
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
> + };
> +
> + jpgdec@...50000 {
> + compatible = "mediatek,mt8195-jpgdec-hw";
> + reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
> + hw_id = <1>;
> + iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
> + <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
> + interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
> + clock-names = "jpgdec";
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
> + };
> +
> + jpgdec@...40000 {
> + compatible = "mediatek,mt8195-jpgdec-hw";
> + reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
> + hw_id = <2>;
> + iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
> + <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
> + <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
> + <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
> + <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
> + <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
> + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
> + clock-names = "jpgdec";
> + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
> + };
> + };
> + };
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