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Message-ID: <CAL_Jsq+0GJBTVkS12XTvUKphMH4XuQ5AS1-QHMw6ULgpWbZBQQ@mail.gmail.com>
Date: Tue, 5 Jul 2022 12:33:57 -0600
From: Rob Herring <robh+dt@...nel.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc: "Viorel Suman (OSS)" <viorel.suman@....nxp.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
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Subject: Re: [PATCH v6 02/14] dt-bindings: pinctrl: imx: Add fsl,scu-iomux
yaml file
On Thu, Jun 30, 2022 at 12:33 PM Krzysztof Kozlowski
<krzysztof.kozlowski@...aro.org> wrote:
>
> On 30/06/2022 14:37, Viorel Suman (OSS) wrote:
> > On 22-06-29 19:53:51, Krzysztof Kozlowski wrote:
> >> On 29/06/2022 18:44, Viorel Suman (OSS) wrote:
> >>> From: Abel Vesa <abel.vesa@....com>
> >>>
> >>> In order to replace the fsl,scu txt file from bindings/arm/freescale,
> >>> we need to split it between the right subsystems. This patch documents
> >>> separately the 'iomux/pinctrl' child node of the SCU main node.
> >>>
> >>> Signed-off-by: Abel Vesa <abel.vesa@....com>
> >>> Signed-off-by: Viorel Suman <viorel.suman@....com>
> >>> ---
> >>> .../bindings/pinctrl/fsl,scu-pinctrl.yaml | 68 +++++++++++++++++++
> >>> 1 file changed, 68 insertions(+)
> >>> create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml
> >>> new file mode 100644
> >>> index 000000000000..76a2e7b28172
> >>> --- /dev/null
> >>> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,scu-pinctrl.yaml
> > [...]
> >>> + fsl,pins:
> >>> + description:
> >>> + each entry consists of 3 integers and represents the pin ID, the mux value
> >>> + and config setting for the pin. The first 2 integers - pin_id and mux_val - are
> >>> + specified using a PIN_FUNC_ID macro, which can be found in
> >>> + <include/dt-bindings/pinctrl/pads-imx8qxp.h>. The last integer CONFIG is
> >>> + the pad setting value like pull-up on this pin. Please refer to the
> >>> + appropriate i.MX8 Reference Manual for detailed CONFIG settings.
> >>> + $ref: /schemas/types.yaml#/definitions/uint32-matrix
> >>
> >> Look at fsl,imx8mq-pinctrl.yaml. Each item is described (items under items).
> >
> > Added them initially, but later dropped because of some logs like
> > "pinctrl@...xxxx: usdhc1grp:fsl,pins:0: [...] is too long" shown by
> > "make dt_binding_check dtbs_check DT_SCHEMA_FILES=[...]/fsl,scu-pinctrl.yaml"
> >
> > Same logs are shown for "fsl,imx8mq-pinctrl.yaml". Will add the items description in the next
> > version.
> >
>
> The fsl,imx8mq-pinctrl.yaml should be correct and I don't see the reason
> why dtschema complains in some of the entries. It's like one define was
> not correct... I'll take a look at this later, but anyway keep the same
> as fsl,imx8mq-pinctrl.yaml even if it complains.
The issue is that 'fsl,pins' is problematic for the new dtb decoding
because it has a variable definition in terms of matrix bounds as each
i.MX platform has its own length (typ 5 or 6). The tools try to work
around it by figuring out which size fits. That works until there are
multiple answers which seems to be what's happening here.
The easiest solution I think is to just strip the constraints in
occurances of this property. I'll look into that.
Rob
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