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Date: Tue, 5 Jul 2022 17:11:42 +0800
From: haibo.chen@....com
To: ashish.kumar@....com, yogeshgaur.83@...il.com, broonie@...nel.org,
robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
han.xu@....com, singh.kuldeep87k@...il.com,
tudor.ambarus@...rochip.com, p.yadav@...com, michael@...le.cc,
miquel.raynal@...tlin.com, richard@....at, vigneshr@...com,
shawnguo@...nel.org, s.hauer@...gutronix.de, kernel@...gutronix.de
Cc: linux-spi@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-mtd@...ts.infradead.org,
festevam@...il.com, linux-imx@....com,
linux-arm-kernel@...ts.infradead.org, haibo.chen@....com,
zhengxunli@...c.com.tw
Subject: [PATCH 10/11] arm64: dts: imx8ulp: add flexspi support
From: Haibo Chen <haibo.chen@....com>
Add flexspi support, and enable the 8 bit TX/RX for the
mx25uw51345gxdi00 spi-nor flash.
Signed-off-by: Haibo Chen <haibo.chen@....com>
---
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts | 34 +++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 20 ++++++++++-
2 files changed, 53 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
index 33e84c4e9ed8..69209b87d432 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -21,6 +21,23 @@ memory@...00000 {
};
};
+&flexspi2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_flexspi2_ptd>;
+ pinctrl-1 = <&pinctrl_flexspi2_ptd>;
+ status = "okay";
+
+ mx25uw51345gxdi00: flash@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <200000000>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ };
+};
+
&lpuart5 {
/* console */
pinctrl-names = "default", "sleep";
@@ -39,6 +56,23 @@ &usdhc0 {
};
&iomuxc1 {
+ pinctrl_flexspi2_ptd: flexspi2ptdgrp {
+ fsl,pins = <
+
+ MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B 0x42
+ MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK 0x42
+ MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3 0x42
+ MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2 0x42
+ MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1 0x42
+ MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0 0x42
+ MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS 0x42
+ MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7 0x42
+ MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6 0x42
+ MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5 0x42
+ MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4 0x42
+ >;
+ };
+
pinctrl_lpuart5: lpuart5grp {
fsl,pins = <
MX8ULP_PAD_PTF14__LPUART5_TX 0x3
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 09f7364dd1d0..4f92c4d6e8c0 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
@@ -141,7 +141,8 @@ soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x0 0x0 0x0 0x40000000>;
+ ranges = <0x0 0x0 0x0 0x40000000>,
+ <0x60000000 0x0 0x60000000 0x1000000>;
per_bridge3: bus@...00000 {
compatible = "simple-bus";
@@ -272,6 +273,23 @@ pcc4: clock-controller@...00000 {
#clock-cells = <1>;
};
+ flexspi2: spi@...10000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,imx8mm-fspi";
+ reg = <0x29810000 0x10000>, <0x60000000 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>,
+ <&pcc4 IMX8ULP_CLK_FLEXSPI2>;
+ clock-names = "fspi", "fspi_en";
+ assigned-clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>;
+ assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV1>;
+ status = "disabled";
+ };
+
+
+
lpi2c6: i2c@...40000 {
compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x29840000 0x10000>;
--
2.25.1
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