linux-kernel - Re: [PATCH v5 0/4] RISC-V: Create unique identification for SoC PMU

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Date:   Wed,  6 Jul 2022 17:50:33 +0100
From:   Will Deacon <will@...nel.org>
To:     Nikita Shubin <nikita.shubin@...uefel.me>
Cc:     catalin.marinas@....com, kernel-team@...roid.com,
        Will Deacon <will@...nel.org>,
        João Mário Domingos 
        <joao.mario@...nico.ulisboa.pt>, linux@...ro.com,
        Namhyung Kim <namhyung@...nel.org>,
        linux-riscv@...ts.infradead.org,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...nel.org>, linux-perf-users@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Anup Patel <anup@...infault.org>,
        Genevieve Chan <genevieve.chan@...rfivetech.com>,
        Nikita Shubin <n.shubin@...ro.com>,
        Mark Rutland <mark.rutland@....com>
Subject: Re: [PATCH v5 0/4] RISC-V: Create unique identification for SoC PMU

On Tue, 28 Jun 2022 14:45:54 +0300, Nikita Shubin wrote:
> From: Nikita Shubin <n.shubin@...ro.com>
> 
> From: Nikita Shubin <n.shubin@...ro.com>
> 
> This series aims to provide matching vendor SoC with corresponded JSON bindings.
> 
> The ID string is proposed to be in form of MVENDORID-MARCHID-MIMPID, for example
> for Sifive Unmatched the corresponding string will be:
> 
> [...]

Applied first patch only to will (for-next/perf), thanks!

[1/4] drivers/perf: riscv_pmu_sbi: perf format
      https://git.kernel.org/will/c/26fabd6d2ffc

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev