linux-kernel - Re: [PATCH] MIPS: smp-mt: enable all hardware interrupts on second VPE

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Date:   Thu, 7 Jul 2022 16:39:30 +0200
From:   Thomas Bogendoerfer <tsbogend@...ha.franken.de>
To:     Martin Blumenstingl <martin.blumenstingl@...glemail.com>
Cc:     Marc Zyngier <maz@...nel.org>,
        Sander Vanheule <sander@...nheule.net>,
        Aleksander Jan Bajkowski <olek2@...pl>,
        Hauke Mehrtens <hauke@...ke-m.de>, git@...ger-koblitz.de,
        linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] MIPS: smp-mt: enable all hardware interrupts on second
 VPE

On Thu, Jul 07, 2022 at 02:57:15PM +0200, Martin Blumenstingl wrote:
> On Thu, Jul 7, 2022 at 12:11 PM Thomas Bogendoerfer
> <tsbogend@...ha.franken.de> wrote:
> [...]
> > > - why can MIPS CPU interrupt 6 and 7 be enabled unconditionally while
> > > 2-5 cannot be enabled unconditionally?
> >
> > 7 is timer interrupt and is usually wired for 34K cpus and 6 is
> > performance counter hopefully handled as well. And I agree that
> > this still isn't the best approach here
> Thanks for this explanation!
> 
> > > - seeing that there's also a mips_gic_present() check in the opposite
> > > case of what Aleksander's patch modifies: does this indicate that
> > > unmasking CPU interrupt lines for VPE 1 is not handled by the MIPS CPU
> > > interrupt controller driver at all at this point (and if so: do you
> > > have any suggestions how to properly fix this)?
> >
> > I haven't checked how GIC is integrated. Iirc it does something similair
> > to Lantiq's irq controller and hides all CPU internal interrupts behind
> > it.
> >
> > So I see two solutions for your problem.
> >
> > 1. Add "mti,cpu-interrupt-controller" to the DT and wire it up
> I think this is the preferred way. I tried this before (if you are
> curious, see [0] and [1]) and it didn't work.
> Are you aware of any MIPS SoC with upstream drivers which do have
> working IRQs on VPE 1?

I don't know of such SoC. Looking at the comment in vsmp_init_secondary()

/* This is Malta specific: IPI,performance and timer interrupts */

there is probably some Malta board using it.

> Or can you point me to the code in
> drivers/irqchip/irq-mips-cpu.c that's responsible for enabling the
> interrupts on VPE 1 (is it simply unmask_mips_irq)?

IMHO there is the problem, irq-mips-cpu.c can only do CPU irq operations
on the same CPU. I've checked MIPS MT specs and it's possible do
modify CP0 registers between VPEs. Using that needs changes in
irq-mips-cpu.c. But mabye that's not woth the effort as probably
all SMP cabable platforms have some multi processort capable
interrupt controller implemented.

I thought about another way solve the issue. By introducing a
new function in smp-mt.c which sets the value of the interrupt
mask for the secondary CPU, which is then used in vsmp_init_secondary().
Not sure if this is worth the effort compared to a .boot_secondary
override.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]