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Date: Fri, 8 Jul 2022 21:33:41 +0100 From: Conor Dooley <mail@...chuod.ie> To: Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>, Palmer Dabbelt <palmer@...osinc.com>, Albert Ou <aou@...s.berkeley.edu>, Sudeep Holla <sudeep.holla@....com>, Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>, "Rafael J . Wysocki" <rafael@...nel.org> Cc: Daire McNamara <daire.mcnamara@...rochip.com>, Conor Dooley <conor.dooley@...rochip.com>, Niklas Cassel <niklas.cassel@....com>, Damien Le Moal <damien.lemoal@...nsource.wdc.com>, Geert Uytterhoeven <geert@...ux-m68k.org>, Zong Li <zong.li@...ive.com>, Emil Renner Berthing <kernel@...il.dk>, Jonas Hahnfeld <hahnjo@...njo.de>, Guo Ren <guoren@...nel.org>, Anup Patel <anup@...infault.org>, Atish Patra <atishp@...shpatra.org>, Heiko Stuebner <heiko@...ech.de>, Philipp Tomsich <philipp.tomsich@...ll.eu>, Rob Herring <robh@...nel.org>, Marc Zyngier <maz@...nel.org>, Viresh Kumar <viresh.kumar@...aro.org>, linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, Brice Goglin <Brice.Goglin@...ia.fr> Subject: [PATCH v2 0/2] Fix RISC-V's arch-topology reporting From: Conor Dooley <conor.dooley@...rochip.com> Hey all, It's my first time messing around with arch/ code at all, let alone more than one arch, so forgive me if I have screwed up how to do a migration like this. The goal here is the fix the incorrectly reported arch topology on RISC-V which seems to have been broken since it was added. cpu, package and thread IDs are all currently reported as -1, so tools like lstopo think systems have multiple threads on the same core when this is not true: https://github.com/open-mpi/hwloc/issues/536 arm64's topology code basically applies to RISC-V too, so it has been made generic along with the removal of MPIDR related code, which appears to be redudant code since '3102bc0e6ac7 ("arm64: topology: Stop using MPIDR for topology information")' replaced the code that actually interacted with MPIDR with default values. I only built tested for arm64, so hopefully it is not broken when used. Testing on both arm64 & !SMP RISC-V would really be appreciated! For V2, I dropped the idea of doing a RISC-V specific implementation followed by a move to the generic code & just went for the more straight forward method of moving to the shared version first. I also dropped the RFC :) Thanks, Conor. Conor Dooley (2): arm64: topology: move store_cpu_topology() to shared code riscv: topology: fix default topology reporting arch/arm64/kernel/topology.c | 40 ------------------------------------ arch/riscv/Kconfig | 2 +- arch/riscv/kernel/smpboot.c | 4 +++- drivers/base/arch_topology.c | 19 +++++++++++++++++ 4 files changed, 23 insertions(+), 42 deletions(-) base-commit: b6f1f2fa2bddd69ff46a190b8120bd440fd50563 -- 2.37.0
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