linux-kernel - Re: [PATCH v1] arm64: dts: qcom: sc7280: Update lpassaudio clock controller for resets

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Message-ID: <CAE-0n51vx8X3+WiOSMx9LnO17uu+5XapYjSG8ybKOS_F_CYAhQ@mail.gmail.com>
Date:   Fri, 8 Jul 2022 13:48:55 -0700
From:   Stephen Boyd <swboyd@...omium.org>
To:     Matthias Kaehlcke <mka@...omium.org>,
        Taniya Das <quic_tdas@...cinc.com>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Douglas Anderson <dianders@...omium.org>,
        Andy Gross <agross@...nel.org>, devicetree@...r.kernel.org,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v1] arm64: dts: qcom: sc7280: Update lpassaudio clock
 controller for resets

Quoting Taniya Das (2022-07-07 00:06:59)
>
> Hi Stephen,
>
> On 6/15/2022 2:08 AM, Stephen Boyd wrote:
> > Quoting Matthias Kaehlcke (2022-06-14 09:51:57)
> >> On Tue, Jun 14, 2022 at 09:41:18PM +0530, Taniya Das wrote:
> >>> The lpass audio supports TX/RX/WSA block resets. The LPASS PIL clock
> >>> driver is not supported and mark it disabled. Also to keep consistency
> >>> update lpasscore to lpass_core.
> >>
> >> There is a driver for "qcom,sc7280-lpasscc", what does it mean that is
> >> isn't supported?
> >>
> >> IIUC one problem is that 'lpasscc@...0000' and 'lpass_aon / clock-controller@...0000'
> >> have overlapping register ranges, so they can't be used together.
> >>
> >> You could just say 'Disable the LPASS PIL clock by default, boards
> >> can enable it if needed'.
> >
> > For the pinctrl driver we added a "qcom,adsp-bypass-mode" property[1] to
> > indicate that the ADSP was being bypassed or not. Can we do the same
> > here and combine the device nodes that have overlapping reg properties?
> >
> > [1] https://lore.kernel.org/r/1654921357-16400-2-git-send-email-quic_srivasam@quicinc.com
>
> Could we take up as a cleanup and take it forward:
> https://lore.kernel.org/lkml/20220614153306.29339-1-quic_tdas@quicinc.com/T/#t
>

I don't think so. The binding would need to change.