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Message-ID: <YsgmkBpk4JBTkjPz@sirena.org.uk>
Date:   Fri, 8 Jul 2022 13:44:00 +0100
From:   Mark Brown <broonie@...nel.org>
To:     Aidan MacDonald <aidanmacdonald.0x0@...il.com>
Cc:     paul@...pouillou.net, lgirdwood@...il.com, perex@...ex.cz,
        tiwai@...e.com, linux-mips@...r.kernel.org,
        alsa-devel@...a-project.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 04/11] ASoC: jz4740-i2s: Handle independent FIFO flush
 bits

On Fri, Jul 08, 2022 at 11:42:57AM +0100, Aidan MacDonald wrote:
> On the JZ4740, there is a single bit that flushes (empties) both
> the transmit and receive FIFO. Later SoCs have independent flush
> bits for each FIFO, which allows us to flush the right FIFO when
> starting up a stream.
> 
> This also fixes a bug: since we were only setting the JZ4740's
> flush bit, which corresponds to the TX FIFO flush bit on other
> SoCs, other SoCs were not having their RX FIFO flushed at all.
> 
> Fixes: 967beb2e8777 ("ASoC: jz4740: Add jz4780 support")

Fixes should generally be at the start of a patch series so they don't
end up depending on other patches needlessly.

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