linux-kernel - Re: [PATCH v5 1/3] clk: qcom: clk-alpha-pll: add support for APSS PLL

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Message-ID: <CAOX2RU4bpd5xAMA-2wFWW9iypbqijkhnwkLZ_gqBorCkyuKegQ@mail.gmail.com>
Date:   Fri, 8 Jul 2022 15:19:19 +0200
From:   Robert Marko <robimarko@...il.com>
To:     Konrad Dybcio <konrad.dybcio@...ainline.org>
Cc:     Andy Gross <agross@...nel.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        krzysztof.kozlowski+dt@...aro.org,
        open list <linux-kernel@...r.kernel.org>,
        linux-arm-msm <linux-arm-msm@...r.kernel.org>,
        linux-clk@...r.kernel.org,
        Devicetree List <devicetree@...r.kernel.org>
Subject: Re: [PATCH v5 1/3] clk: qcom: clk-alpha-pll: add support for APSS PLL

On Wed, 6 Jul 2022 at 15:14, Konrad Dybcio <konrad.dybcio@...ainline.org> wrote:
>
>
>
> On 5.07.2022 21:10, Robert Marko wrote:
> > APSS PLL type will be used by the IPQ8074 APSS driver for providing the
> > CPU core clocks and enabling CPU Frequency scaling.
> >
> > This is ported from the downstream 5.4 kernel.
> >
> > Signed-off-by: Robert Marko <robimarko@...il.com>
> > ---
> >  drivers/clk/qcom/clk-alpha-pll.c | 12 ++++++++++++
> >  drivers/clk/qcom/clk-alpha-pll.h |  1 +
> >  2 files changed, 13 insertions(+)
> >
> > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> > index 4406cf609aae..8270363ff98e 100644
> > --- a/drivers/clk/qcom/clk-alpha-pll.c
> > +++ b/drivers/clk/qcom/clk-alpha-pll.c
> > @@ -154,6 +154,18 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
> >               [PLL_OFF_TEST_CTL_U] = 0x30,
> >               [PLL_OFF_TEST_CTL_U1] = 0x34,
> >       },
> > +     [CLK_ALPHA_PLL_TYPE_APSS] = {
> The name is surely not correct, can somebody from qcom chime in
> and suggest what it should be?

Hi Konrad,
That is how Qualcomm refers to the type in the downstream 4.4 and 5.4 kernels.
I dont have any other reference to the name unless somebody from
Qualcomm can chime in.

Regards,
Robert
>
> Konrad
> > +             [PLL_OFF_L_VAL] = 0x08,
> > +             [PLL_OFF_ALPHA_VAL] = 0x10,
> > +             [PLL_OFF_ALPHA_VAL_U] = 0xff,
> > +             [PLL_OFF_USER_CTL] = 0x18,
> > +             [PLL_OFF_USER_CTL_U] = 0xff,
> > +             [PLL_OFF_CONFIG_CTL] = 0x20,
> > +             [PLL_OFF_CONFIG_CTL_U] = 0x24,
> > +             [PLL_OFF_TEST_CTL] = 0x30,
> > +             [PLL_OFF_TEST_CTL_U] = 0x34,
> > +             [PLL_OFF_STATUS] = 0x28,
> > +     },
> >  };
> >  EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
> >
> > diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
> > index 6e9907deaf30..626fdf80336d 100644
> > --- a/drivers/clk/qcom/clk-alpha-pll.h
> > +++ b/drivers/clk/qcom/clk-alpha-pll.h
> > @@ -18,6 +18,7 @@ enum {
> >       CLK_ALPHA_PLL_TYPE_AGERA,
> >       CLK_ALPHA_PLL_TYPE_ZONDA,
> >       CLK_ALPHA_PLL_TYPE_LUCID_EVO,
> > +     CLK_ALPHA_PLL_TYPE_APSS,
> >       CLK_ALPHA_PLL_TYPE_MAX,
> >  };
> >