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Message-ID: <20220708142937.1120121-1-conor.dooley@microchip.com>
Date: Fri, 8 Jul 2022 15:29:34 +0100
From: Conor Dooley <conor.dooley@...rochip.com>
To: Thierry Reding <thierry.reding@...il.com>,
Uwe Kleine-König
<u.kleine-koenig@...gutronix.de>,
"Lee Jones" <lee.jones@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@...aro.org>
CC: Daire McNamara <daire.mcnamara@...rochip.com>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-pwm@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
Conor Dooley <conor.dooley@...rochip.com>
Subject: [PATCH v4 0/4] Microchip soft ip corePWM driver
Hey Uwe, all,
Added some extra patches so I have a cover letter this time.
You pointed out that I was overriding npwmcells in the driver and I
realised that the dt & binding were not correct so I have added two
simple patches to deal with that. The dts patch I will take in my tree
once the binding is applied.
For the maintainers entry, I mentioned before that I have several
changes in-flight for it. We are late(ish) in the cycle so I doubt
you'll be applying this for v5.20, but in the off chance you do - I
would be happy to send it (with your Ack) alongside an i2c addition
that is "deferred".
In your review of v3, you had a lot of comments about the period and
duty cycle calculations, so I have had another run at them. I converted
the period calculation to "search" from the bottom up for the suitable
prescale value. The duty cycle calculation has been fixed - the problem
was exactly what I suspected in my replies to your review. I had to block
the use of a 0xFF period_steps register value (which I think should be
covered by the updated comment and limitation #2).
Beyond that, I have rebased on -next and converted to the devm_ stuff
in probe that was recently added & dropped remove() - as requested.
I added locking to protect the period racing, changed the #defines and
switched to returning -EINVAL when the period is locked to a value
greater than that requested.
Thanks,
Conor.
Conor Dooley (4):
dt-bindings: pwm: fix microchip corePWM's pwm-cells
riscv: dts: fix the icicle's #pwm-cells
pwm: add microchip soft ip corePWM driver
MAINTAINERS: add pwm to PolarFire SoC entry
.../bindings/pwm/microchip,corepwm.yaml | 4 +-
MAINTAINERS | 1 +
.../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 2 +-
.../dts/microchip/mpfs-tysom-m-fabric.dtsi | 18 +
.../riscv/boot/dts/microchip/mpfs-tysom-m.dts | 185 +++++++++
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-microchip-core.c | 355 ++++++++++++++++++
8 files changed, 574 insertions(+), 2 deletions(-)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
create mode 100644 drivers/pwm/pwm-microchip-core.c
base-commit: 088b9c375534d905a4d337c78db3b3bfbb52c4a0
--
2.36.1
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