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Message-ID: <20220709141715.834713-1-Perry.Yuan@amd.com>
Date: Sat, 9 Jul 2022 10:17:15 -0400
From: Perry Yuan <Perry.Yuan@....com>
To: <rafael.j.wysocki@...el.com>, <viresh.kumar@...aro.org>,
<Ray.Huang@....com>
CC: <Deepak.Sharma@....com>, <Mario.Limonciello@....com>,
<Nathan.Fontenot@....com>, <Alexander.Deucher@....com>,
<Jinzhou.Su@....com>, <Xinmei.Huang@....com>,
<Xiaojian.Du@....com>, <Li.Meng@....com>,
<linux-pm@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
Perry Yuan <Perry.Yuan@....com>
Subject: [PATCH v2 01/14] x86/msr: Add the MSR definition for AMD CPPC hardware control.
This MSR can be used for controlling whether the CPU boost state
is enabled in the hardware.
AMD Processor Programming Reference (PPR)
Link: https://www.amd.com/system/files/TechDocs/40332.pdf [p1095]
Link: https://www.amd.com/system/files/TechDocs/56569-A1-PUB.zip [p162]
Signed-off-by: Perry Yuan <Perry.Yuan@....com>
---
arch/x86/include/asm/msr-index.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index d27e0581b777..869508de8269 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -548,6 +548,7 @@
#define MSR_AMD_CPPC_CAP2 0xc00102b2
#define MSR_AMD_CPPC_REQ 0xc00102b3
#define MSR_AMD_CPPC_STATUS 0xc00102b4
+#define MSR_AMD_CPPC_HW_CTL 0xc0010015
#define AMD_CPPC_LOWEST_PERF(x) (((x) >> 0) & 0xff)
#define AMD_CPPC_LOWNONLIN_PERF(x) (((x) >> 8) & 0xff)
--
2.25.1
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