[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <762b3f80-a925-0a00-1386-b190fe17ea59@microchip.com>
Date: Mon, 11 Jul 2022 12:56:16 +0000
From: <Conor.Dooley@...rochip.com>
To: <ben.dooks@...ive.com>, <Conor.Dooley@...rochip.com>,
<robin.murphy@....com>, <hch@....de>
CC: <linux-kernel@...r.kernel.org>, <iommu@...ts.linux.dev>,
<iommu@...ts.linux-foundation.org>, <sudip.mukherjee@...ive.com>,
<jude.onyenegecha@...ive.com>, <m.szyprowski@...sung.com>,
<Daire.McNamara@...rochip.com>
Subject: Re: [PATCH] swiotlb: ensure io_tlb_default_mem spinlock always
initialised
On 11/07/2022 13:45, Ben Dooks wrote:
> On 11/07/2022 12:52, Conor.Dooley@...rochip.com wrote:
>>
>>
>> On 11/07/2022 12:01, Robin Murphy wrote:
>>> On 2022-07-11 11:42, Ben Dooks wrote:
>>>> On 11/07/2022 11:39, Christoph Hellwig wrote:
>>>>> On Mon, Jul 11, 2022 at 11:24:51AM +0100, Ben Dooks wrote:
>>>>>> On 11/07/2022 11:21, Christoph Hellwig wrote:
>>>>>>> On Mon, Jul 11, 2022 at 11:07:17AM +0100, Robin Murphy wrote:
>>>>>>>> If none of your peripherals should need SWIOTLB, then the fact that
>>>>>>>> you're ending up in swiotlb_map() at all is a clear sign that
>>>>>>>> something's wrong. Most likely someone's forgotten to set their DMA
>>>>>>>> masks correctly.
>>>>>>>
>>>>>>> Yes.
>>>>>>
>>>>>> Possibly, we had at least one driver which attempted to set a 32 bit
>>>>>> DMA mask which had to be removed as the DMA layer accepts this but
>>>>>> since there is no DMA32 memory the allocator then just fails.
>>>>>>
>>>>>> I expect the above may need to be a separate discussion(s) of how to
>>>>>> default the DMA mask and how to stop the implicit acceptance of setting
>>>>>> a 32-bit DMA mask.
>>>>>
>>>>> No. Linux simply assumes you can do 32-bit DMA and this won't
>>>>> change. So we'll need to fix your platform to support swiotlb
>>>>> eventually.
>>>>
>>>> Ok, is there any examples currently in the kernel that have no memory
>>>> in the DMA32 zone that do use swiotlb?
>>>
>>> The arm64 code originally made an assumption that a system with that kind of memory layout would use a DMA offset in the interconnect, and so placed ZONE_DMA32 in the first 4GB of available RAM rather than actual physical address space. The only relatively mainstream platform we subsequently saw with all RAM above 32 bits was AMD Seattle, which also *didn't* use a DMA offset, so it "worked" by virtue of this bodge in the sense that allocations didn't fail, but DMA transactions would then disappear off into nowhere when the device truncated the MSBs of whatever too-big DMA address it was given.
>>>
>>> I think that stuff's long gone by now, and if any of handful of remaining Seattle users plug in a 32-bit PCIe device and try to use it with the IOMMU disabled, they'll probably see the fireworks as intended.
>>>
>>> Much as we'd like to make DMA an explicit opt-in for all drivers, that's something which can only really be solved 30 years ago.
>>
>>
>> Out of curiosity Ben, can you shed any more light on the platform?
>
> Not at the moment, sorry.
No worries. FWIW, if you do end up doing anything with no-DMA32
platforms keep me CCed. I've previously hit no-DMA32 related issues
on PolarFire SoC, so I'd like to test anything that you may end up
working on.
Thanks,
Conor.
Powered by blists - more mailing lists