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Message-ID: <CAD=FV=WMJ1BX-uA4eavocbAGjpSsEYhoYGSha9gBYsqAXhHX-g@mail.gmail.com>
Date: Mon, 11 Jul 2022 07:57:29 -0700
From: Doug Anderson <dianders@...omium.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Cc: Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Konrad Dybcio <konrad.dybcio@...ainline.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Martin Botka <martin.botka@...ainline.org>,
linux-arm-msm <linux-arm-msm@...r.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>, LKML <linux-kernel@...r.kernel.org>,
Bhupesh Sharma <bhupesh.sharma@...aro.org>
Subject: Re: [PATCH RFT] arm64: dts: qcom: sm6125: fix SDHCI CQE reg names
Hi,
On Mon, Jul 11, 2022 at 1:26 AM Krzysztof Kozlowski
<krzysztof.kozlowski@...aro.org> wrote:
>
> SM6125 comes with SDCC (SDHCI controller) v5, so the second range of
> registers is cqhci, not core.
>
> Fixes: cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125")
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
>
> ---
>
> Not tested on hardware, but no practical impact is expected, because
> supports-cqe is not defined.
Maybe the schema should enforce this? If "cqhci" is in reg-names then
you must have supports-cqe and vice versa?
> ---
> arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> index 77bff81af433..7664ef7e4da9 100644
> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> @@ -438,7 +438,7 @@ rpm_msg_ram: sram@...0000 {
> sdhc_1: mmc@...4000 {
> compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5";
> reg = <0x04744000 0x1000>, <0x04745000 0x1000>;
> - reg-names = "hc", "core";
> + reg-names = "hc", "cqhci";
Another possible fix would be to just delete the second register
range. Then it could be added back in once "supports-cqe" was added.
-Doug
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