linux-kernel - [PATCH 1/2] drm/amd/pm: Add GFXOFF registers for vangogh

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20220711191953.145518-2-andrealmeid@igalia.com>
Date:   Mon, 11 Jul 2022 16:19:52 -0300
From:   André Almeida <andrealmeid@...lia.com>
To:     Alex Deucher <alexander.deucher@....com>,
        'Christian König' <christian.koenig@....com>,
        'Pan Xinhui' <Xinhui.Pan@....com>,
        David Airlie <airlied@...ux.ie>,
        Daniel Vetter <daniel@...ll.ch>,
        Hawking Zhang <Hawking.Zhang@....com>,
        Tao Zhou <tao.zhou1@....com>,
        Felix Kuehling <Felix.Kuehling@....com>,
        Jack Xiao <Jack.Xiao@....com>, amd-gfx@...ts.freedesktop.org,
        dri-devel@...ts.freedesktop.org, linux-kernel@...r.kernel.org
Cc:     kernel-dev@...lia.com,
        André Almeida <andrealmeid@...lia.com>
Subject: [PATCH 1/2] drm/amd/pm: Add GFXOFF registers for vangogh

Add register values to access GFXOFF data for vangogh GPU.

Signed-off-by: André Almeida <andrealmeid@...lia.com>
---
 .../pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h   | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h
index 8361ebd8d876..9c7b0004d842 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h
@@ -279,4 +279,16 @@ typedef enum {
 #define TILE_ISPPRE_MASK    ((1<<6) | (1<<7))
 #define TILE_ISPPOST_MASK   ((1<<8) | (1<<9))
 
+// Registers related to GFXOFF
+// addressBlock: smuio_smuio_SmuSmuioDec
+// base address: 0x5a000
+#define mmSMUIO_GFX_MISC_CNTL			0x00c5
+#define mmSMUIO_GFX_MISC_CNTL_BASE_IDX		0
+
+//SMUIO_GFX_MISC_CNTL
+#define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT	0x0
+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT		0x1
+#define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK	0x00000001L
+#define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK		0x00000006L
+
 #endif
-- 
2.37.0