lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Tue, 12 Jul 2022 16:21:33 +0100 From: Mauro Carvalho Chehab <mchehab@...nel.org> To: unlisted-recipients:; (no To-header on input) Cc: Chris Wilson <chris.p.wilson@...el.com>, Andi Shyti <andi.shyti@...ux.intel.com>, Daniel Vetter <daniel@...ll.ch>, Daniele Ceraolo Spurio <daniele.ceraolospurio@...el.com>, Dave Airlie <airlied@...hat.com>, David Airlie <airlied@...ux.ie>, Jani Nikula <jani.nikula@...ux.intel.com>, John Harrison <John.C.Harrison@...el.com>, Joonas Lahtinen <joonas.lahtinen@...ux.intel.com>, Lucas De Marchi <lucas.demarchi@...el.com>, Matt Roper <matthew.d.roper@...el.com>, Rodrigo Vivi <rodrigo.vivi@...el.com>, Tvrtko Ursulin <tvrtko.ursulin@...ux.intel.com>, dri-devel@...ts.freedesktop.org, intel-gfx@...ts.freedesktop.org, linux-kernel@...r.kernel.org, stable@...r.kernel.org, Mauro Carvalho Chehab <mchehab@...nel.org>, Thomas Hellström <thomas.hellstrom@...ux.intel.com> Subject: [PATCH v5 2/2] drm/i915/gt: Serialize TLB invalidates with GT resets From: Chris Wilson <chris.p.wilson@...el.com> Avoid trying to invalidate the TLB in the middle of performing an engine reset, as this may result in the reset timing out. Currently, the TLB invalidate is only serialised by its own mutex, forgoing the uncore lock, but we can take the uncore->lock as well to serialise the mmio access, thereby serialising with the GDRST. Tested on a NUC5i7RYB, BIOS RYBDWi35.86A.0380.2019.0517.1530 with i915 selftest/hangcheck. Cc: stable@...r.kernel.org # v4.4 and upper Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") Reported-by: Mauro Carvalho Chehab <mchehab@...nel.org> Tested-by: Mauro Carvalho Chehab <mchehab@...nel.org> Reviewed-by: Mauro Carvalho Chehab <mchehab@...nel.org> Signed-off-by: Chris Wilson <chris.p.wilson@...el.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@...ux.intel.com> Reviewed-by: Andi Shyti <andi.shyti@...ux.intel.com> Acked-by: Thomas Hellström <thomas.hellstrom@...ux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@...nel.org> --- See [PATCH v5 0/2] at: https://lore.kernel.org/all/cover.1657639152.git.mchehab@kernel.org/ drivers/gpu/drm/i915/gt/intel_gt.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 8da3314bb6bf..68c2b0d8f187 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -952,6 +952,20 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) mutex_lock(>->tlb_invalidate_lock); intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL); + spin_lock_irq(&uncore->lock); /* serialise invalidate with GT reset */ + + for_each_engine(engine, gt, id) { + struct reg_and_bit rb; + + rb = get_reg_and_bit(engine, regs == gen8_regs, regs, num); + if (!i915_mmio_reg_offset(rb.reg)) + continue; + + intel_uncore_write_fw(uncore, rb.reg, rb.bit); + } + + spin_unlock_irq(&uncore->lock); + for_each_engine(engine, gt, id) { /* * HW architecture suggest typical invalidation time at 40us, @@ -966,7 +980,6 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) if (!i915_mmio_reg_offset(rb.reg)) continue; - intel_uncore_write_fw(uncore, rb.reg, rb.bit); if (__intel_wait_for_register_fw(uncore, rb.reg, rb.bit, 0, timeout_us, timeout_ms, -- 2.36.1
Powered by blists - more mailing lists