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Message-ID: <8614fd96-94ff-a04f-01a2-9f3b6337dcb6@linaro.org>
Date: Tue, 12 Jul 2022 10:21:33 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: "Peng Fan (OSS)" <peng.fan@....nxp.com>, robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org, shawnguo@...nel.org,
s.hauer@...gutronix.de, l.stach@...gutronix.de
Cc: kernel@...gutronix.de, festevam@...il.com, linux-imx@....com,
laurent.pinchart@...asonboard.com, marex@...x.de,
paul.elder@...asonboard.com, aford173@...il.com,
Markus.Niebel@...tq-group.com, alexander.stein@...tq-group.com,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, aisheng.dong@....com,
Peng Fan <peng.fan@....com>
Subject: Re: [PATCH 2/6] dt-bindings: soc: imx: add i.MX8MP vpu blk ctrl
On 12/07/2022 10:21, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@....com>
>
> i.MX8MP VPU blk ctrl module has similar design as i.MX8MM, so reuse
> the i.MX8MM VPU blk ctrl yaml file.
>
> Signed-off-by: Peng Fan <peng.fan@....com>
> ---
> .../soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml | 17 ++++++++++++++---
> include/dt-bindings/power/imx8mp-power.h | 4 ++++
> 2 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
> index 26487daa64d9..edbd267cdd67 100644
> --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
> +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml
> @@ -4,20 +4,22 @@
> $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml#
> $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> -title: NXP i.MX8MM VPU blk-ctrl
> +title: NXP i.MX8MM/P VPU blk-ctrl
>
> maintainers:
> - Lucas Stach <l.stach@...gutronix.de>
>
> description:
> - The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to
> + The i.MX8MM/P VPU blk-ctrl is a top-level peripheral providing access to
> the NoC and ensuring proper power sequencing of the VPU peripherals
> located in the VPU domain of the SoC.
>
> properties:
> compatible:
> items:
> - - const: fsl,imx8mm-vpu-blk-ctrl
> + - enum:
> + - fsl,imx8mm-vpu-blk-ctrl
> + - fsl,imx8mp-vpu-blk-ctrl
> - const: syscon
>
> reg:
> @@ -47,6 +49,15 @@ properties:
> - const: g2
> - const: h1
>
> + interconnects:
> + maxItems: 3
You should describe the items, because g1/g2/h1 are quite cryptic.
Best regards,
Krzysztof
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