linux-kernel - Re: [PATCH v1 2/2] pinctrl: nuvoton: add NPCM8XX pinctrl and GPIO driver

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Message-ID: <d8bc7a14-a9c5-4d34-997a-48a8d27c5edd@linaro.org>
Date:   Wed, 13 Jul 2022 16:28:57 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Tomer Maimon <tmaimon77@...il.com>
Cc:     Avi Fishman <avifishman70@...il.com>,
        Tali Perry <tali.perry1@...il.com>,
        Joel Stanley <joel@....id.au>,
        Patrick Venture <venture@...gle.com>,
        Nancy Yuen <yuenn@...gle.com>,
        Benjamin Fair <benjaminfair@...gle.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Jonathan Neuschäfer <j.neuschaefer@....net>,
        zhengbin13@...wei.com, OpenBMC Maillist <openbmc@...ts.ozlabs.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        devicetree <devicetree@...r.kernel.org>
Subject: Re: [PATCH v1 2/2] pinctrl: nuvoton: add NPCM8XX pinctrl and GPIO
 driver

On 13/07/2022 15:35, Tomer Maimon wrote:

>>> +static int npcm8xx_pinctrl_probe(struct platform_device *pdev)
>>> +{
>>> +     struct npcm8xx_pinctrl *pctrl;
>>> +     int ret;
>>> +
>>> +     pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
>>> +     if (!pctrl)
>>> +             return -ENOMEM;
>>> +
>>> +     pctrl->dev = &pdev->dev;
>>> +     dev_set_drvdata(&pdev->dev, pctrl);
>>> +
>>> +     pctrl->gcr_regmap =
>>> +             syscon_regmap_lookup_by_compatible("nuvoton,npcm845-gcr");
>>
>> No. Use property. By this patchset, I would expect that you learnt from
>> previous mistakes around this. Why repeating the same trouble second time?
> You suggest to use phandle property like nuvoton,sysgcr even that the
> NPCM8XX pin controller driver is used only NPCM8XX SoC, so the only
> GCR node in the NPCM8XX SoC is nuvoton,npcm845-gcr?

Yes. The previous case (reset driver, AFAIR) was also about driver used
only in one SoC, wasn't it?

Best regards,
Krzysztof