linux-kernel - linux-next: manual merge of the tip tree with Linus' tree

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Message-ID: <20220713150854.68b2d129@canb.auug.org.au>
Date:   Wed, 13 Jul 2022 15:08:54 +1000
From:   Stephen Rothwell <sfr@...b.auug.org.au>
To:     Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>,
        "H. Peter Anvin" <hpa@...or.com>,
        Peter Zijlstra <peterz@...radead.org>
Cc:     Borislav Petkov <bp@...e.de>,
        "Chang S. Bae" <chang.seok.bae@...el.com>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Linux Next Mailing List <linux-next@...r.kernel.org>
Subject: linux-next: manual merge of the tip tree with Linus' tree

Hi all,

Today's linux-next merge of the tip tree got a conflict in:

  drivers/idle/intel_idle.c

between commit:

  bf5835bcdb96 ("intel_idle: Disable IBRS during long idle")

from Linus' tree and commit:

  f08ef9057b7b ("intel_idle: Add a new flag to initialize the AMX state")

from the tip tree.

I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging.  You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.

-- 
Cheers,
Stephen Rothwell

diff --cc drivers/idle/intel_idle.c
index f5c6802aa6c3,8a19ba1c2c1b..000000000000
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@@ -53,9 -52,9 +53,10 @@@
  #include <linux/moduleparam.h>
  #include <asm/cpu_device_id.h>
  #include <asm/intel-family.h>
 +#include <asm/nospec-branch.h>
  #include <asm/mwait.h>
  #include <asm/msr.h>
+ #include <asm/fpu/api.h>
  
  #define INTEL_IDLE_VERSION "0.5.1"
  
@@@ -107,12 -106,11 +108,17 @@@ static unsigned int mwait_substates __i
   */
  #define CPUIDLE_FLAG_ALWAYS_ENABLE	BIT(15)
  
 +/*
 + * Disable IBRS across idle (when KERNEL_IBRS), is exclusive vs IRQ_ENABLE
 + * above.
 + */
 +#define CPUIDLE_FLAG_IBRS		BIT(16)
 +
+ /*
+  * Initialize large xstate for the C6-state entrance.
+  */
 -#define CPUIDLE_FLAG_INIT_XSTATE	BIT(16)
++#define CPUIDLE_FLAG_INIT_XSTATE	BIT(17)
+ 
  /*
   * MWAIT takes an 8-bit "hint" in EAX "suggesting"
   * the C-state (top nibble) and sub-state (bottom nibble)
@@@ -167,24 -165,13 +173,31 @@@ static __cpuidle int intel_idle_irq(str
  	return ret;
  }
  
 +static __cpuidle int intel_idle_ibrs(struct cpuidle_device *dev,
 +				     struct cpuidle_driver *drv, int index)
 +{
 +	bool smt_active = sched_smt_active();
 +	u64 spec_ctrl = spec_ctrl_current();
 +	int ret;
 +
 +	if (smt_active)
 +		wrmsrl(MSR_IA32_SPEC_CTRL, 0);
 +
 +	ret = __intel_idle(dev, drv, index);
 +
 +	if (smt_active)
 +		wrmsrl(MSR_IA32_SPEC_CTRL, spec_ctrl);
 +
 +	return ret;
 +}
 +
+ static __cpuidle int intel_idle_xstate(struct cpuidle_device *dev,
+ 				       struct cpuidle_driver *drv, int index)
+ {
+ 	fpu_idle_fpregs();
+ 	return __intel_idle(dev, drv, index);
+ }
+ 
  /**
   * intel_idle_s2idle - Ask the processor to enter the given idle state.
   * @dev: cpuidle device of the target CPU.
@@@ -1845,12 -1837,9 +1863,15 @@@ static void __init intel_idle_init_csta
  		if (cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_IRQ_ENABLE)
  			drv->states[drv->state_count].enter = intel_idle_irq;
  
 +		if (cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS) &&
 +		    cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_IBRS) {
 +			WARN_ON_ONCE(cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_IRQ_ENABLE);
 +			drv->states[drv->state_count].enter = intel_idle_ibrs;
 +		}
 +
+ 		if (cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_INIT_XSTATE)
+ 			drv->states[drv->state_count].enter = intel_idle_xstate;
+ 
  		if ((disabled_states_mask & BIT(drv->state_count)) ||
  		    ((icpu->use_acpi || force_use_acpi) &&
  		     intel_idle_off_by_default(mwait_hint) &&

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