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Message-ID: <7c4eaa8e-2812-b805-c81b-9964a5cb6b52@huawei.com>
Date: Wed, 13 Jul 2022 15:37:13 +0800
From: "guomengqi (A)" <guomengqi3@...wei.com>
To: Florian Fainelli <f.fainelli@...il.com>,
<gregkh@...uxfoundation.org>, <jirislaby@...nel.org>,
<rjui@...adcom.com>, <sbranden@...adcom.com>,
<bcm-kernel-feedback-list@...adcom.com>, <nsaenz@...nel.org>,
<athierry@...hat.com>, <linux-serial@...r.kernel.org>,
<linux-rpi-kernel@...ts.infradead.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>
CC: <xuqiang36@...wei.com>
Subject: Re: [PATCH -next] drivers/tty/serial: Add missing
clk_disable_unprepare()
Hi Florian,
Yes I found it's better to use title of same style. I did not pay
attention to this.
I will send a new version of this patch.
Thank you!
在 2022/7/12 11:35, Florian Fainelli 写道:
>
>
> On 6/16/2022 7:58 PM, 'Guo Mengqi' via BCM-KERNEL-FEEDBACK-LIST,PDL
> wrote:
>> Add missing clk_disable_unprepare() when get clk rate fails.
>>
>> Reported-by: Hulk Robot <hulkci@...wei.com>
>> Signed-off-by: Guo Mengqi <guomengqi3@...wei.com>
>
> Looks about right, can we use the same prefix as the majority of other
> changes:
>
> serial: 8250_bcm2835aux: Add missing clk_disable_unprepare()
>
> and slap a:
>
> Fixes: fcc446c8aa63 ("serial: 8250_bcm2835aux: Add ACPI support")
>
> Thanks!
>
>> ---
>> drivers/tty/serial/8250/8250_bcm2835aux.c | 6 ++++--
>> 1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/tty/serial/8250/8250_bcm2835aux.c
>> b/drivers/tty/serial/8250/8250_bcm2835aux.c
>> index 2a1226a78a0c..21939bb44613 100644
>> --- a/drivers/tty/serial/8250/8250_bcm2835aux.c
>> +++ b/drivers/tty/serial/8250/8250_bcm2835aux.c
>> @@ -166,8 +166,10 @@ static int bcm2835aux_serial_probe(struct
>> platform_device *pdev)
>> uartclk = clk_get_rate(data->clk);
>> if (!uartclk) {
>> ret = device_property_read_u32(&pdev->dev,
>> "clock-frequency", &uartclk);
>> - if (ret)
>> - return dev_err_probe(&pdev->dev, ret, "could not get clk
>> rate\n");
>> + if (ret) {
>> + dev_err_probe(&pdev->dev, ret, "could not get clk rate\n");
>> + goto dis_clk;
>> + }
>> }
>> /* the HW-clock divider for bcm2835aux is 8,
>
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