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Message-ID: <CAHp75Ve9bhCMznLemFBc0K04S2vT8gv=aTkHZ6DVc9RZwsPVpw@mail.gmail.com>
Date:   Wed, 13 Jul 2022 11:54:51 +0200
From:   Andy Shevchenko <andy.shevchenko@...il.com>
To:     Horatiu Vultur <horatiu.vultur@...rochip.com>
Cc:     "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Linus Walleij <linus.walleij@...aro.org>,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        kavyasree.kotagiri@...rochip.com,
        Colin Foster <colin.foster@...advantage.com>,
        Microchip Linux Driver Support <UNGLinuxDriver@...rochip.com>,
        Maxime Chevallier <maxime.chevallier@...tlin.com>,
        Michael Walle <michael@...le.cc>
Subject: Re: [PATCH v4 2/2] pinctrl: ocelot: Fix pincfg

On Tue, Jul 12, 2022 at 9:46 PM Horatiu Vultur
<horatiu.vultur@...rochip.com> wrote:
>
> The blamed commit changed to use regmaps instead of __iomem. But it
> didn't update the register offsets to be at word offset, so it uses byte
> offset.
> Another issue with the same commit is that it has a limit of 32 registers
> which is incorrect. The sparx5 has 64 while lan966x has 77.

Reviewed-by: Andy Shevchenko <andy.shevchenko@...il.com>

> Fixes: 076d9e71bcf8 ("pinctrl: ocelot: convert pinctrl to regmap")
> Signed-off-by: Horatiu Vultur <horatiu.vultur@...rochip.com>
> ---
>  drivers/pinctrl/pinctrl-ocelot.c | 19 +++++++++++++------
>  1 file changed, 13 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c
> index 873bba245522..c5a9f87f0c49 100644
> --- a/drivers/pinctrl/pinctrl-ocelot.c
> +++ b/drivers/pinctrl/pinctrl-ocelot.c
> @@ -1334,7 +1334,9 @@ static int ocelot_hw_get_value(struct ocelot_pinctrl *info,
>                 const struct ocelot_pincfg_data *opd = info->pincfg_data;
>                 u32 regcfg;
>
> -               ret = regmap_read(info->pincfg, pin, &regcfg);
> +               ret = regmap_read(info->pincfg,
> +                                 pin * regmap_get_reg_stride(info->pincfg),
> +                                 &regcfg);
>                 if (ret)
>                         return ret;
>
> @@ -1366,14 +1368,18 @@ static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr,
>         u32 val;
>         int ret;
>
> -       ret = regmap_read(info->pincfg, regaddr, &val);
> +       ret = regmap_read(info->pincfg,
> +                         regaddr * regmap_get_reg_stride(info->pincfg),
> +                         &val);
>         if (ret)
>                 return ret;
>
>         val &= ~clrbits;
>         val |= setbits;
>
> -       ret = regmap_write(info->pincfg, regaddr, val);
> +       ret = regmap_write(info->pincfg,
> +                          regaddr * regmap_get_reg_stride(info->pincfg),
> +                          val);
>
>         return ret;
>  }
> @@ -1932,7 +1938,8 @@ static const struct of_device_id ocelot_pinctrl_of_match[] = {
>         {},
>  };
>
> -static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev)
> +static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev,
> +                                                  const struct ocelot_pinctrl *info)
>  {
>         void __iomem *base;
>
> @@ -1940,7 +1947,7 @@ static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev)
>                 .reg_bits = 32,
>                 .val_bits = 32,
>                 .reg_stride = 4,
> -               .max_register = 32,
> +               .max_register = info->desc->npins * 4,
>                 .name = "pincfg",
>         };
>
> @@ -2008,7 +2015,7 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
>
>         /* Pinconf registers */
>         if (info->desc->confops) {
> -               pincfg = ocelot_pinctrl_create_pincfg(pdev);
> +               pincfg = ocelot_pinctrl_create_pincfg(pdev, info);
>                 if (IS_ERR(pincfg))
>                         dev_dbg(dev, "Failed to create pincfg regmap\n");
>                 else
> --
> 2.33.0
>


-- 
With Best Regards,
Andy Shevchenko

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