linux-kernel - Re: [perf] unchecked MSR access error: WRMSR to 0x689 in intel_pmu_lbr

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Date:   Thu, 14 Jul 2022 13:50:20 -0400
From:   "Liang, Kan" <kan.liang@...ux.intel.com>
To:     Vince Weaver <vincent.weaver@...ne.edu>
Cc:     Pawan Gupta <pawan.kumar.gupta@...ux.intel.com>,
        linux-kernel@...r.kernel.org,
        Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...nel.org>,
        Namhyung Kim <namhyung@...nel.org>
Subject: Re: [perf] unchecked MSR access error: WRMSR to 0x689 in
 intel_pmu_lbr_restore



On 2022-07-14 12:12 p.m., Vince Weaver wrote:
> On Tue, 12 Jul 2022, Liang, Kan wrote:
> 
>>
>> Could you please apply the below patch, reboot to the patched kernel and
>> share the dmesg log?
> 
> here's the info with your patch applied:
> 
> [    0.000000] microcode: microcode updated early to revision 0x28, date = 2019-11-12
> ...
> [    1.460296] NO HLE NO RTM. LBR has tsx 0


Thanks.

The issue should be introduced by the commit 1ac7fd8159a8
("perf/x86/intel/lbr: Support LBR format V7").
The quirk is invoked before the intel_pmu_lbr_init(), which set the
x86_pmu.lbr_has_tsx.

I will send out a patch to fix it shortly.

Thanks,
Kan

> [    1.468217] Haswell events, 16-deep LBR, full-width counters, Intel PMU driver.
> [    1.472292] ... version:                3
> [    1.476275] ... bit width:              48
> [    1.480275] ... generic registers:      4
> [    1.484276] ... value mask:             0000ffffffffffff
> [    1.488277] ... max period:             00007fffffffffff
> [    1.492277] ... fixed-purpose events:   3
> [    1.496271] ... event mask:             000000070000000f
> 
> Vince