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Message-ID: <mhng-efe2b7ce-e803-4a61-91b7-ca9c302a33bc@palmer-ri-x1c9>
Date: Thu, 14 Jul 2022 15:04:03 -0700 (PDT)
From: Palmer Dabbelt <palmer@...belt.com>
To: mail@...chuod.ie
CC: robh+dt@...nel.org, krzysztof.kozlowski+dt@...aro.org,
Paul Walmsley <paul.walmsley@...ive.com>,
aou@...s.berkeley.edu, daire.mcnamara@...rochip.com,
conor.dooley@...rochip.com, niklas.cassel@....com,
damien.lemoal@...nsource.wdc.com, geert@...ux-m68k.org,
zong.li@...ive.com, kernel@...il.dk, hahnjo@...njo.de,
devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, Brice.Goglin@...ia.fr
Subject: Re: [PATCH 4/5] riscv: dts: microchip: Add mpfs' topology information
On Tue, 05 Jul 2022 12:04:35 PDT (-0700), mail@...chuod.ie wrote:
> From: Conor Dooley <conor.dooley@...rochip.com>
>
> The mpfs has no cpu-map node, so tools like hwloc cannot correctly
> parse the topology. Add the node using the existing node labels.
>
> Reported-by: Brice Goglin <Brice.Goglin@...ia.fr>
> Link: https://github.com/open-mpi/hwloc/issues/536
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> ---
> arch/riscv/boot/dts/microchip/mpfs.dtsi | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> index 45efd35d50c5..0a17d30bb3f2 100644
> --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
> @@ -138,6 +138,30 @@ cpu4_intc: interrupt-controller {
> interrupt-controller;
> };
> };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> +
> + core1 {
> + cpu = <&cpu1>;
> + };
> +
> + core2 {
> + cpu = <&cpu2>;
> + };
> +
> + core3 {
> + cpu = <&cpu3>;
> + };
> +
> + core4 {
> + cpu = <&cpu4>;
> + };
> + };
> + };
> };
>
> refclk: mssrefclk {
In case anyone is following along: this patch got split out from the
rest of the series and ended up in the Microchip DT PR for 5.20.
I've taken the other four into for-next.
Thanks!
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