linux-kernel - Re: [PATCH v2] Subject: x86/PAT: Report PAT on CPUs that support PAT without MTRR

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Date:   Thu, 14 Jul 2022 08:28:38 +0200
From:   Jan Beulich <jbeulich@...e.com>
To:     Juergen Gross <jgross@...e.com>
Cc:     Dave Hansen <dave.hansen@...ux.intel.com>,
        Andy Lutomirski <luto@...nel.org>,
        Peter Zijlstra <peterz@...radead.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        x86@...nel.org, "H. Peter Anvin" <hpa@...or.com>,
        Dan Williams <dan.j.williams@...el.com>,
        "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
        Tom Lendacky <thomas.lendacky@....com>,
        Jane Chu <jane.chu@...cle.com>,
        Tianyu Lan <Tianyu.Lan@...rosoft.com>,
        Randy Dunlap <rdunlap@...radead.org>,
        Sean Christopherson <seanjc@...gle.com>,
        xen-devel@...ts.xenproject.org,
        Chuck Zmudzinski <brchuckz@....com>,
        linux-kernel@...r.kernel.org, stable@...r.kernel.org
Subject: Re: [PATCH v2] Subject: x86/PAT: Report PAT on CPUs that support PAT
 without MTRR

On 14.07.2022 07:40, Juergen Gross wrote:
> On 13.07.22 03:36, Chuck Zmudzinski wrote:
>> @@ -292,7 +294,7 @@ void init_cache_modes(void)
>>   		rdmsrl(MSR_IA32_CR_PAT, pat);
>>   	}
>>   
>> -	if (!pat) {
>> +	if (!pat || pat_force_disabled) {
> 
> Can we just remove this modification and ...
> 
>>   		/*
>>   		 * No PAT. Emulate the PAT table that corresponds to the two
>>   		 * cache bits, PWT (Write Through) and PCD (Cache Disable).
>> @@ -313,6 +315,16 @@ void init_cache_modes(void)
>>   		 */
>>   		pat = PAT(0, WB) | PAT(1, WT) | PAT(2, UC_MINUS) | PAT(3, UC) |
>>   		      PAT(4, WB) | PAT(5, WT) | PAT(6, UC_MINUS) | PAT(7, UC);
>> +	} else if (!pat_bp_enabled) {
> 
> ... use
> 
> +	} else if (!pat_bp_enabled && !pat_force_disabled) {
> 
> here?
> 
> This will result in the desired outcome in all cases IMO: If PAT wasn't
> disabled via "nopat" and the PAT MSR has a non-zero value (from BIOS or
> Hypervisor) and PAT has been disabled implicitly (e.g. due to lack of
> MTRR), then PAT will be set to "enabled" again.

Just to mention it explicitly: If the value _read_ from the MSR is zero,
we're hosed anyway, as then we can only express a single memory type (UC)
in all PTEs. The zero case we mean to deal with is when reading the MSR
wasn't valid to try.

Jan