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Date:   Fri, 15 Jul 2022 16:51:27 +0800
From:   CK Hu <ck.hu@...iatek.com>
To:     Bo-Chen Chen <rex-bc.chen@...iatek.com>, <chunkuang.hu@...nel.org>,
        <p.zabel@...gutronix.de>, <daniel@...ll.ch>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <mripard@...nel.org>,
        <tzimmermann@...e.de>, <matthias.bgg@...il.com>, <deller@....de>,
        <airlied@...ux.ie>
CC:     <msp@...libre.com>, <granquet@...libre.com>,
        <jitao.shi@...iatek.com>, <wenst@...omium.org>,
        <angelogioacchino.delregno@...labora.com>,
        <liangxu.xu@...iatek.com>, <dri-devel@...ts.freedesktop.org>,
        <linux-mediatek@...ts.infradead.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-fbdev@...r.kernel.org>,
        <Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: Re: [PATCH v14 05/10] drm/mediatek: Add MT8195 Embedded DisplayPort
 driver

Hi, Bo-Chen:

On Tue, 2022-07-12 at 19:12 +0800, Bo-Chen Chen wrote:
> From: Markus Schneider-Pargmann <msp@...libre.com>
> 
> This patch adds a embedded displayport driver for the MediaTek mt8195
> SoC.
> 
> It supports the MT8195, the embedded DisplayPort units. It offers
> DisplayPort 1.4 with up to 4 lanes.
> 
> The driver creates a child device for the phy. The child device will
> never exist without the parent being active. As they are sharing a
> register range, the parent passes a regmap pointer to the child so
> that
> both can work with the same register range. The phy driver sets
> device
> data that is read by the parent to get the phy device that can be
> used
> to control the phy properties.
> 
> This driver is based on an initial version by
> Jitao shi <jitao.shi@...iatek.com>
> 
> Signed-off-by: Markus Schneider-Pargmann <msp@...libre.com>
> Signed-off-by: Guillaume Ranquet <granquet@...libre.com>
> Signed-off-by: Bo-Chen Chen <rex-bc.chen@...iatek.com>
> ---

[snip]

> +static void mtk_dp_hpd_sink_event(struct mtk_dp *mtk_dp)
> +{
> +	ssize_t ret;
> +	u8 sink_count;
> +	u8 link_status[DP_LINK_STATUS_SIZE] = {};
> +	u32 sink_count_reg = DP_SINK_COUNT_ESI;
> +	u32 link_status_reg = DP_LANE0_1_STATUS;
> +
> +	ret = drm_dp_dpcd_readb(&mtk_dp->aux, sink_count_reg,
> &sink_count);

According to your last reply, if drm_dp_dpcd_readb() fail, we could
skip below statement. So this just for error checking? If so, the next
drm_dp_dpcd_read() would also do the error checking, so the checking
here is redundant.

Regards,
CK

> +	if (ret < 1) {
> +		drm_err(mtk_dp->drm_dev, "Read sink count failed\n");
> +		return;
> +	}
> +
> +	drm_dbg(mtk_dp->drm_dev,
> +		"read sink count from dpcd: %d\n", sink_count);
> +
> +	ret = drm_dp_dpcd_read(&mtk_dp->aux, link_status_reg,
> link_status,
> +			       sizeof(link_status));
> +	if (!ret) {
> +		drm_err(mtk_dp->drm_dev, "Read link status failed\n");
> +		return;
> +	}
> +
> +	if (!drm_dp_channel_eq_ok(link_status, mtk_dp-
> >train_info.lane_count)) {
> +		drm_err(mtk_dp->drm_dev, "Channel EQ failed\n");
> +		return;
> +	}
> +
> +	if (link_status[1] & DP_REMOTE_CONTROL_COMMAND_PENDING)
> +		drm_dp_dpcd_writeb(&mtk_dp->aux,
> DP_DEVICE_SERVICE_IRQ_VECTOR,
> +				   DP_REMOTE_CONTROL_COMMAND_PENDING);
> +}
> +

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