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Date:   Fri, 15 Jul 2022 19:00:21 +0800
From:   Allen-KH Cheng <allen-kh.cheng@...iatek.com>
To:     Matthias Brugger <matthias.bgg@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
CC:     <Project_Global_Chrome_Upstream_Group@...iatek.com>,
        <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-mediatek@...ts.infradead.org>,
        "Chen-Yu Tsai" <wenst@...omium.org>, <hsinyi@...omium.org>,
        Allen-KH Cheng <allen-kh.cheng@...iatek.com>
Subject: [PATCH] dt-bindings: mediatek: Add #reset-cells to mt8186 sys-clock controller

MediaTek system clock controller includes reset controller and needs
to specify the #reset-cells property.

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@...iatek.com>
---
 .../bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml      | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
index 0886e2e335bb..e6bdc79f058b 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
@@ -39,6 +39,9 @@ properties:
   '#clock-cells':
     const: 1
 
+  '#reset-cells':
+    const: 1
+
 required:
   - compatible
   - reg
@@ -51,4 +54,5 @@ examples:
         compatible = "mediatek,mt8186-topckgen", "syscon";
         reg = <0x10000000 0x1000>;
         #clock-cells = <1>;
+        #reset-cells = <1>;
     };
-- 
2.18.0

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