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Date: Fri, 15 Jul 2022 10:52:40 -0400
From: Jason Baron <jbaron@...mai.com>
To: Josh Hant <joshuahant@...il.com>
Cc: linux-edac@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] EDAC/ie31200: Add Skylake-S support
On 7/12/22 06:21, Josh Hant wrote:
> Add device IDs for Skylake-S CPUs according to datasheet.
>
> Signed-off-by: Josh Hant <joshuahant@...il.com>
> ---
> Hi Jason,
>
> Sorry for the late response. I added the missing check you asked for. I
> kept the documentation the same for now. I found the register in table 3
> of the original document I linked. If you would rather I provide the one
> you linked, I'll do that in the next patch.
Yes, I think the link I had was useful, for example it had register offsets
for things like ECCERRLOG which I didn't see in the reference you linked.
Maybe just include both?
>
> I confirmed that the name and size in /proc/meminfo is consistent with
> what is in /sys/devices/system/edac/mc/mc0.
Ok, great. Yeah let's just add the extra documentation link and then the
patch seems fine.
Thanks,
-Jason
>
> Thanks
> -Josh
> drivers/edac/ie31200_edac.c | 27 ++++++++++++++++++---------
> 1 file changed, 18 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c
> index 9a9ff5ad611a..3d322603bce8 100644
> --- a/drivers/edac/ie31200_edac.c
> +++ b/drivers/edac/ie31200_edac.c
> @@ -20,11 +20,14 @@
> * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
> * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
> * 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
> + * 190f: 6th Gen Core Dual-Core Processor Host Bridge/DRAM Registers
> + * 191f: 6th Gen Core Quad-Core Processor Host Bridge/DRAM Registers
> * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers
> *
> * Based on Intel specification:
> * https://urldefense.com/v3/__https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf__;!!GjvTz_vk!R59Q1Bnf9RyI0ZIv2OAIqpD_lPa6_sdWaeFoH595ZLDCCri1SLs1ZCbrgr53QjTZAyLVmoiv9oZ-6raD$
> * https://urldefense.com/v3/__http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html__;!!GjvTz_vk!R59Q1Bnf9RyI0ZIv2OAIqpD_lPa6_sdWaeFoH595ZLDCCri1SLs1ZCbrgr53QjTZAyLVmoiv9m6NRBGA$
> + * https://urldefense.com/v3/__https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-2.pdf__;!!GjvTz_vk!R59Q1Bnf9RyI0ZIv2OAIqpD_lPa6_sdWaeFoH595ZLDCCri1SLs1ZCbrgr53QjTZAyLVmoiv9gF6-zMQ$
> * https://urldefense.com/v3/__https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html__;!!GjvTz_vk!R59Q1Bnf9RyI0ZIv2OAIqpD_lPa6_sdWaeFoH595ZLDCCri1SLs1ZCbrgr53QjTZAyLVmoiv9q7dFz1H$
> * https://urldefense.com/v3/__https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html__;!!GjvTz_vk!R59Q1Bnf9RyI0ZIv2OAIqpD_lPa6_sdWaeFoH595ZLDCCri1SLs1ZCbrgr53QjTZAyLVmoiv9vbMAhyi$
> *
> @@ -53,15 +56,17 @@
> #define ie31200_printk(level, fmt, arg...) \
> edac_printk(level, "ie31200", fmt, ##arg)
>
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x1918
> -#define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x5918
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x190F
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x1918
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F
> +#define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x5918
>
> /* Coffee Lake-S */
> #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00
> @@ -80,6 +85,8 @@
> #define DEVICE_ID_SKYLAKE_OR_LATER(did) \
> (((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_8) || \
> ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) || \
> + ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_10) || \
> + ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_11) || \
> (((did) & PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK) == \
> PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK))
>
> @@ -577,6 +584,8 @@ static const struct pci_device_id ie31200_pci_tbl[] = {
> { PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> + { PCI_VEND_DEV(INTEL, IE31200_HB_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> + { PCI_VEND_DEV(INTEL, IE31200_HB_11), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
> --
> 2.34.3
>
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