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Date: Sat, 16 Jul 2022 00:53:18 +0800
From: Jisheng Zhang <jszhang@...nel.org>
To: Emil Renner Berthing <emil.renner.berthing@...onical.com>
Cc: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Andrey Ryabinin <ryabinin.a.a@...il.com>,
Alexander Potapenko <glider@...gle.com>,
Andrey Konovalov <andreyknvl@...il.com>,
Dmitry Vyukov <dvyukov@...gle.com>,
Vincenzo Frascino <vincenzo.frascino@....com>,
Alexandre Ghiti <alexandre.ghiti@...onical.com>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
kasan-dev@...glegroups.com, Anup Patel <anup@...infault.org>
Subject: Re: [PATCH v5 2/2] riscv: turn pgtable_l4|[l5]_enabled to static key
for RV64
On Fri, Jul 15, 2022 at 05:04:38PM +0200, Emil Renner Berthing wrote:
> On Fri, 15 Jul 2022 at 15:59, Jisheng Zhang <jszhang@...nel.org> wrote:
> > On a specific HW platform, pgtable_l4|[l5]_enabled won't change after
> > boot, and the check sits at hot code path, this characteristic makes it
> > suitable for optimization with static key.
> >
> > _pgtable_l4|[l5]_enabled is used very early during boot, even is used
> > with MMU off, so the static key mechanism isn't ready. For this case,
> > we use another static key _pgtable_lx_ready to indicate whether we
> > have finalised pgtable_l4|[l5]_enabled or not, then fall back to
> > _pgtable_l4|[l5]_enabled_early bool.
> >
> > Signed-off-by: Jisheng Zhang <jszhang@...nel.org>
> > Reviewed-by: Anup Patel <anup@...infault.org>
> > ---
> > arch/riscv/include/asm/pgalloc.h | 16 ++++----
> > arch/riscv/include/asm/pgtable-32.h | 3 ++
> > arch/riscv/include/asm/pgtable-64.h | 60 ++++++++++++++++++---------
> > arch/riscv/include/asm/pgtable.h | 5 +--
> > arch/riscv/kernel/cpu.c | 4 +-
> > arch/riscv/mm/init.c | 64 ++++++++++++++++++-----------
> > arch/riscv/mm/kasan_init.c | 16 ++++----
> > 7 files changed, 103 insertions(+), 65 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/pgalloc.h b/arch/riscv/include/asm/pgalloc.h
> > index 947f23d7b6af..0280eeb4756f 100644
> > --- a/arch/riscv/include/asm/pgalloc.h
> > +++ b/arch/riscv/include/asm/pgalloc.h
> > @@ -41,7 +41,7 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
> >
> > static inline void p4d_populate(struct mm_struct *mm, p4d_t *p4d, pud_t *pud)
> > {
> > - if (pgtable_l4_enabled) {
> > + if (pgtable_l4_enabled()) {
> > unsigned long pfn = virt_to_pfn(pud);
> >
> > set_p4d(p4d, __p4d((pfn << _PAGE_PFN_SHIFT) | _PAGE_TABLE));
> > @@ -51,7 +51,7 @@ static inline void p4d_populate(struct mm_struct *mm, p4d_t *p4d, pud_t *pud)
> > static inline void p4d_populate_safe(struct mm_struct *mm, p4d_t *p4d,
> > pud_t *pud)
> > {
> > - if (pgtable_l4_enabled) {
> > + if (pgtable_l4_enabled()) {
> > unsigned long pfn = virt_to_pfn(pud);
> >
> > set_p4d_safe(p4d,
> > @@ -61,7 +61,7 @@ static inline void p4d_populate_safe(struct mm_struct *mm, p4d_t *p4d,
> >
> > static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, p4d_t *p4d)
> > {
> > - if (pgtable_l5_enabled) {
> > + if (pgtable_l5_enabled()) {
> > unsigned long pfn = virt_to_pfn(p4d);
> >
> > set_pgd(pgd, __pgd((pfn << _PAGE_PFN_SHIFT) | _PAGE_TABLE));
> > @@ -71,7 +71,7 @@ static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, p4d_t *p4d)
> > static inline void pgd_populate_safe(struct mm_struct *mm, pgd_t *pgd,
> > p4d_t *p4d)
> > {
> > - if (pgtable_l5_enabled) {
> > + if (pgtable_l5_enabled()) {
> > unsigned long pfn = virt_to_pfn(p4d);
> >
> > set_pgd_safe(pgd,
> > @@ -82,7 +82,7 @@ static inline void pgd_populate_safe(struct mm_struct *mm, pgd_t *pgd,
> > #define pud_alloc_one pud_alloc_one
> > static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
> > {
> > - if (pgtable_l4_enabled)
> > + if (pgtable_l4_enabled())
> > return __pud_alloc_one(mm, addr);
> >
> > return NULL;
> > @@ -91,7 +91,7 @@ static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
> > #define pud_free pud_free
> > static inline void pud_free(struct mm_struct *mm, pud_t *pud)
> > {
> > - if (pgtable_l4_enabled)
> > + if (pgtable_l4_enabled())
> > __pud_free(mm, pud);
> > }
> >
> > @@ -100,7 +100,7 @@ static inline void pud_free(struct mm_struct *mm, pud_t *pud)
> > #define p4d_alloc_one p4d_alloc_one
> > static inline p4d_t *p4d_alloc_one(struct mm_struct *mm, unsigned long addr)
> > {
> > - if (pgtable_l5_enabled) {
> > + if (pgtable_l5_enabled()) {
> > gfp_t gfp = GFP_PGTABLE_USER;
> >
> > if (mm == &init_mm)
> > @@ -120,7 +120,7 @@ static inline void __p4d_free(struct mm_struct *mm, p4d_t *p4d)
> > #define p4d_free p4d_free
> > static inline void p4d_free(struct mm_struct *mm, p4d_t *p4d)
> > {
> > - if (pgtable_l5_enabled)
> > + if (pgtable_l5_enabled())
> > __p4d_free(mm, p4d);
> > }
> >
> > diff --git a/arch/riscv/include/asm/pgtable-32.h b/arch/riscv/include/asm/pgtable-32.h
> > index 59ba1fbaf784..1ef52079179a 100644
> > --- a/arch/riscv/include/asm/pgtable-32.h
> > +++ b/arch/riscv/include/asm/pgtable-32.h
> > @@ -17,6 +17,9 @@
> >
> > #define MAX_POSSIBLE_PHYSMEM_BITS 34
> >
> > +#define pgtable_l5_enabled() 0
> > +#define pgtable_l4_enabled() 0
> > +
> > /*
> > * rv32 PTE format:
> > * | XLEN-1 10 | 9 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
> > diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
> > index 5c2aba5efbd0..edfff00d8ca3 100644
> > --- a/arch/riscv/include/asm/pgtable-64.h
> > +++ b/arch/riscv/include/asm/pgtable-64.h
> > @@ -8,18 +8,38 @@
> >
> > #include <linux/bits.h>
> > #include <linux/const.h>
> > +#include <linux/jump_label.h>
> > #include <asm/errata_list.h>
> >
> > -extern bool pgtable_l4_enabled;
> > -extern bool pgtable_l5_enabled;
> > +extern bool _pgtable_l5_enabled_early;
> > +extern bool _pgtable_l4_enabled_early;
> > +extern struct static_key_false _pgtable_l5_enabled;
> > +extern struct static_key_false _pgtable_l4_enabled;
> > +extern struct static_key_false _pgtable_lx_ready;
>
> It amounts to the same, but I wonder if we ought to use the
> DECLARE_STATIC_KEY_FALSE macro here.
Thanks for the hint, will send out a newer version soon. Before
that, I will wait a bit for other review feedbacks.
Thanks
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