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Message-ID: <CAGsJ_4z0z0mUfuEbyfj7HxB4pBNdkv5igi1rfccithnSB7Q5gA@mail.gmail.com>
Date: Tue, 19 Jul 2022 08:14:41 +1200
From: Barry Song <21cnbao@...il.com>
To: Matthew Wilcox <willy@...radead.org>
Cc: Andrew Morton <akpm@...ux-foundation.org>,
Anshuman Khandual <anshuman.khandual@....com>,
Catalin Marinas <catalin.marinas@....com>,
LAK <linux-arm-kernel@...ts.infradead.org>,
Linux-MM <linux-mm@...ck.org>,
Steven Price <steven.price@....com>,
Will Deacon <will@...nel.org>,
Andrea Arcangeli <aarcange@...hat.com>,
郭健 <guojian@...o.com>,
hanchuanhua <hanchuanhua@...o.com>,
Johannes Weiner <hannes@...xchg.org>,
Hugh Dickins <hughd@...gle.com>,
LKML <linux-kernel@...r.kernel.org>,
Minchan Kim <minchan@...nel.org>,
Yang Shi <shy828301@...il.com>,
Barry Song <v-songbaohua@...o.com>,
Ying Huang <ying.huang@...el.com>,
张诗明(Simon Zhang)
<zhangshiming@...o.com>
Subject: Re: [RESEND PATCH v3] arm64: enable THP_SWAP for arm64
On Tue, Jul 19, 2022 at 4:06 AM Matthew Wilcox <willy@...radead.org> wrote:
>
> On Mon, Jul 18, 2022 at 09:00:50PM +1200, Barry Song wrote:
> > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> > index 1652a9800ebe..e1c540e80eec 100644
> > --- a/arch/arm64/Kconfig
> > +++ b/arch/arm64/Kconfig
> > @@ -101,6 +101,7 @@ config ARM64
> > select ARCH_WANT_HUGETLB_PAGE_OPTIMIZE_VMEMMAP
> > select ARCH_WANT_LD_ORPHAN_WARN
> > select ARCH_WANTS_NO_INSTR
> > + select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES
>
> Can't you avoid all the other changes by simply doing:
>
> select ARCH_WANTS_THP_SWAP if ARM64_4K_PAGES && !ARM64_MTE
>
> > select ARCH_HAS_UBSAN_SANITIZE_ALL
> > select ARM_AMBA
> > select ARM_ARCH_TIMER
Nope. as we also enable ARM64_MTE on platforms without mte.
ARMv8.5 based processors introduce the Memory Tagging Extension
(MTE) feature but the Kconfig is default Y for platforms before 8.5.
arm64 usually detects the cpufeature rather than depending on
static build configuration.
> > diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> > index 0b6632f18364..78d6f6014bfb 100644
> > --- a/arch/arm64/include/asm/pgtable.h
> > +++ b/arch/arm64/include/asm/pgtable.h
> > @@ -45,6 +45,12 @@
> > __flush_tlb_range(vma, addr, end, PUD_SIZE, false, 1)
> > #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
> >
> > +static inline bool arch_thp_swp_supported(void)
> > +{
> > + return !system_supports_mte();
> > +}
> > +#define arch_thp_swp_supported arch_thp_swp_supported
> > +
> > /*
> > * Outside of a few very special situations (e.g. hibernation), we always
> > * use broadcast TLB invalidation instructions, therefore a spurious page
> > diff --git a/include/linux/huge_mm.h b/include/linux/huge_mm.h
> > index de29821231c9..4ddaf6ad73ef 100644
> > --- a/include/linux/huge_mm.h
> > +++ b/include/linux/huge_mm.h
> > @@ -461,4 +461,16 @@ static inline int split_folio_to_list(struct folio *folio,
> > return split_huge_page_to_list(&folio->page, list);
> > }
> >
> > +/*
> > + * archs that select ARCH_WANTS_THP_SWAP but don't support THP_SWP due to
> > + * limitations in the implementation like arm64 MTE can override this to
> > + * false
> > + */
> > +#ifndef arch_thp_swp_supported
> > +static inline bool arch_thp_swp_supported(void)
> > +{
> > + return true;
> > +}
> > +#endif
> > +
> > #endif /* _LINUX_HUGE_MM_H */
> > diff --git a/mm/swap_slots.c b/mm/swap_slots.c
> > index 2a65a89b5b4d..10b94d64cc25 100644
> > --- a/mm/swap_slots.c
> > +++ b/mm/swap_slots.c
> > @@ -307,7 +307,7 @@ swp_entry_t folio_alloc_swap(struct folio *folio)
> > entry.val = 0;
> >
> > if (folio_test_large(folio)) {
> > - if (IS_ENABLED(CONFIG_THP_SWAP))
> > + if (IS_ENABLED(CONFIG_THP_SWAP) && arch_thp_swp_supported())
> > get_swap_pages(1, &entry, folio_nr_pages(folio));
> > goto out;
> > }
> > --
> > 2.25.1
> >
> >
Thanks
Barry
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